From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752535AbbKAK37 (ORCPT ); Sun, 1 Nov 2015 05:29:59 -0500 Received: from terminus.zytor.com ([198.137.202.10]:45284 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752480AbbKAK3a (ORCPT ); Sun, 1 Nov 2015 05:29:30 -0500 Date: Sun, 1 Nov 2015 02:28:30 -0800 From: tip-bot for Wan Zongshun Message-ID: Cc: hpa@zytor.com, mingo@kernel.org, tony.luck@intel.com, bp@suse.de, Vincent.Wan@amd.com, ray.huang@amd.com, dvlasenk@redhat.com, bp@alien8.de, tglx@linutronix.de, aravind.gopalakrishnan@amd.com, peterz@infradead.org, linux-kernel@vger.kernel.org, torvalds@linux-foundation.org, luto@kernel.org Reply-To: Vincent.Wan@amd.com, tglx@linutronix.de, bp@alien8.de, dvlasenk@redhat.com, ray.huang@amd.com, linux-kernel@vger.kernel.org, peterz@infradead.org, aravind.gopalakrishnan@amd.com, torvalds@linux-foundation.org, luto@kernel.org, hpa@zytor.com, mingo@kernel.org, bp@suse.de, tony.luck@intel.com In-Reply-To: <1446207099-24948-4-git-send-email-bp@alien8.de> References: <1446207099-24948-4-git-send-email-bp@alien8.de> To: linux-tip-commits@vger.kernel.org Subject: [tip:x86/cpu] x86/cpu: Add CLZERO detection Git-Commit-ID: 2167ceabf34163727ca4e283c0f030e3960932e5 X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit-ID: 2167ceabf34163727ca4e283c0f030e3960932e5 Gitweb: http://git.kernel.org/tip/2167ceabf34163727ca4e283c0f030e3960932e5 Author: Wan Zongshun AuthorDate: Fri, 30 Oct 2015 13:11:39 +0100 Committer: Ingo Molnar CommitDate: Sun, 1 Nov 2015 11:26:23 +0100 x86/cpu: Add CLZERO detection AMD Fam17h processors introduce support for the CLZERO instruction. It zeroes out the 64 byte cache line specified in RAX. Add the bit here to allow /proc/cpuinfo to list the feature. Boris: we're adding this as a separate ->x86_capability leaf because CPUID_80000008_EBX is going to contain more feature bits and it will fill out with time. Signed-off-by: Wan Zongshun Signed-off-by: Aravind Gopalakrishnan [ Wrap code in patch form, fix comments. ] Signed-off-by: Borislav Petkov Cc: Andy Lutomirski Cc: Borislav Petkov Cc: Denys Vlasenko Cc: H. Peter Anvin Cc: Huang Rui Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: Tony Luck Link: http://lkml.kernel.org/r/1446207099-24948-4-git-send-email-bp@alien8.de Signed-off-by: Ingo Molnar --- arch/x86/include/asm/cpufeature.h | 5 ++++- arch/x86/kernel/cpu/common.c | 1 + 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index 9727b3b..e4f8010 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -12,7 +12,7 @@ #include #endif -#define NCAPINTS 13 /* N 32-bit words worth of info */ +#define NCAPINTS 14 /* N 32-bit words worth of info */ #define NBUGINTS 1 /* N 32-bit bug flags */ /* @@ -255,6 +255,9 @@ /* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (edx), word 12 */ #define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring if 1 */ +/* AMD-defined CPU features, CPUID level 0x80000008 (ebx), word 13 */ +#define X86_FEATURE_CLZERO (13*32+0) /* CLZERO instruction */ + /* * BUG word(s) */ diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index de22ea7..4ddd780 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -670,6 +670,7 @@ void get_cpu_cap(struct cpuinfo_x86 *c) c->x86_virt_bits = (eax >> 8) & 0xff; c->x86_phys_bits = eax & 0xff; + c->x86_capability[13] = cpuid_ebx(0x80000008); } #ifdef CONFIG_X86_32 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))