From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752212AbdKHLG4 (ORCPT ); Wed, 8 Nov 2017 06:06:56 -0500 Received: from terminus.zytor.com ([65.50.211.136]:55389 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751534AbdKHLGx (ORCPT ); Wed, 8 Nov 2017 06:06:53 -0500 Date: Wed, 8 Nov 2017 02:59:49 -0800 From: tip-bot for Ricardo Neri Message-ID: Cc: luto@kernel.org, torvalds@linux-foundation.org, shuah@kernel.org, bp@suse.de, linux-kernel@vger.kernel.org, mst@redhat.com, mingo@kernel.org, bp@alien8.de, brgerst@gmail.com, vbabka@suse.cz, paul.gortmaker@windriver.com, ravi.v.shankar@intel.com, dvlasenk@redhat.com, fenghua.yu@intel.com, slaoub@gmail.com, cmetcalf@mellanox.com, ray.huang@amd.com, mhiramat@kernel.org, jpoimboe@redhat.com, peterz@infradead.org, akpm@linux-foundation.org, dave.hansen@linux.intel.com, tony.luck@intel.com, pbonzini@redhat.com, tglx@linutronix.de, jslaby@suse.cz, corbet@lwn.net, hpa@zytor.com, ricardo.neri-calderon@linux.intel.com Reply-To: dave.hansen@linux.intel.com, akpm@linux-foundation.org, peterz@infradead.org, jpoimboe@redhat.com, tglx@linutronix.de, tony.luck@intel.com, pbonzini@redhat.com, jslaby@suse.cz, ricardo.neri-calderon@linux.intel.com, hpa@zytor.com, corbet@lwn.net, bp@alien8.de, brgerst@gmail.com, mingo@kernel.org, linux-kernel@vger.kernel.org, mst@redhat.com, torvalds@linux-foundation.org, bp@suse.de, shuah@kernel.org, luto@kernel.org, paul.gortmaker@windriver.com, vbabka@suse.cz, dvlasenk@redhat.com, ravi.v.shankar@intel.com, mhiramat@kernel.org, cmetcalf@mellanox.com, ray.huang@amd.com, slaoub@gmail.com, fenghua.yu@intel.com In-Reply-To: <1509935277-22138-7-git-send-email-ricardo.neri-calderon@linux.intel.com> References: <1509935277-22138-7-git-send-email-ricardo.neri-calderon@linux.intel.com> To: linux-tip-commits@vger.kernel.org Subject: [tip:x86/asm] x86/cpufeature: Add User-Mode Instruction Prevention definitions Git-Commit-ID: 3522c2a6a4f341058b8291326a945e2a2d2aaf55 X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit-ID: 3522c2a6a4f341058b8291326a945e2a2d2aaf55 Gitweb: https://git.kernel.org/tip/3522c2a6a4f341058b8291326a945e2a2d2aaf55 Author: Ricardo Neri AuthorDate: Sun, 5 Nov 2017 18:27:51 -0800 Committer: Ingo Molnar CommitDate: Wed, 8 Nov 2017 11:16:21 +0100 x86/cpufeature: Add User-Mode Instruction Prevention definitions User-Mode Instruction Prevention is a security feature present in new Intel processors that, when set, prevents the execution of a subset of instructions if such instructions are executed in user mode (CPL > 0). Attempting to execute such instructions causes a general protection exception. The subset of instructions comprises: * SGDT - Store Global Descriptor Table * SIDT - Store Interrupt Descriptor Table * SLDT - Store Local Descriptor Table * SMSW - Store Machine Status Word * STR - Store Task Register This feature is also added to the list of disabled-features to allow a cleaner handling of build-time configuration. Signed-off-by: Ricardo Neri Reviewed-by: Thomas Gleixner Reviewed-by: Borislav Petkov Cc: Andrew Morton Cc: Andy Lutomirski Cc: Borislav Petkov Cc: Brian Gerst Cc: Chen Yucong Cc: Chris Metcalf Cc: Dave Hansen Cc: Denys Vlasenko Cc: Fenghua Yu Cc: H. Peter Anvin Cc: Huang Rui Cc: Jiri Slaby Cc: Jonathan Corbet Cc: Josh Poimboeuf Cc: Linus Torvalds Cc: Masami Hiramatsu Cc: Michael S. Tsirkin Cc: Paolo Bonzini Cc: Paul Gortmaker Cc: Peter Zijlstra Cc: Ravi V. Shankar Cc: Shuah Khan Cc: Tony Luck Cc: Vlastimil Babka Cc: ricardo.neri@intel.com Link: http://lkml.kernel.org/r/1509935277-22138-7-git-send-email-ricardo.neri-calderon@linux.intel.com Signed-off-by: Ingo Molnar --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/disabled-features.h | 8 +++++++- arch/x86/include/uapi/asm/processor-flags.h | 2 ++ 3 files changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index cdf5be8..c0b0e9e 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -296,6 +296,7 @@ /* Intel-defined CPU features, CPUID level 0x00000007:0 (ECX), word 16 */ #define X86_FEATURE_AVX512VBMI (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/ +#define X86_FEATURE_UMIP (16*32+ 2) /* User Mode Instruction Protection */ #define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */ #define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */ #define X86_FEATURE_AVX512_VBMI2 (16*32+ 6) /* Additional AVX512 Vector Bit Manipulation Instructions */ diff --git a/arch/x86/include/asm/disabled-features.h b/arch/x86/include/asm/disabled-features.h index c10c912..14d6d50 100644 --- a/arch/x86/include/asm/disabled-features.h +++ b/arch/x86/include/asm/disabled-features.h @@ -16,6 +16,12 @@ # define DISABLE_MPX (1<<(X86_FEATURE_MPX & 31)) #endif +#ifdef CONFIG_X86_INTEL_UMIP +# define DISABLE_UMIP 0 +#else +# define DISABLE_UMIP (1<<(X86_FEATURE_UMIP & 31)) +#endif + #ifdef CONFIG_X86_64 # define DISABLE_VME (1<<(X86_FEATURE_VME & 31)) # define DISABLE_K6_MTRR (1<<(X86_FEATURE_K6_MTRR & 31)) @@ -63,7 +69,7 @@ #define DISABLED_MASK13 0 #define DISABLED_MASK14 0 #define DISABLED_MASK15 0 -#define DISABLED_MASK16 (DISABLE_PKU|DISABLE_OSPKE|DISABLE_LA57) +#define DISABLED_MASK16 (DISABLE_PKU|DISABLE_OSPKE|DISABLE_LA57|DISABLE_UMIP) #define DISABLED_MASK17 0 #define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 18) diff --git a/arch/x86/include/uapi/asm/processor-flags.h b/arch/x86/include/uapi/asm/processor-flags.h index 53b4ca5..7e1e730 100644 --- a/arch/x86/include/uapi/asm/processor-flags.h +++ b/arch/x86/include/uapi/asm/processor-flags.h @@ -105,6 +105,8 @@ #define X86_CR4_OSFXSR _BITUL(X86_CR4_OSFXSR_BIT) #define X86_CR4_OSXMMEXCPT_BIT 10 /* enable unmasked SSE exceptions */ #define X86_CR4_OSXMMEXCPT _BITUL(X86_CR4_OSXMMEXCPT_BIT) +#define X86_CR4_UMIP_BIT 11 /* enable UMIP support */ +#define X86_CR4_UMIP _BITUL(X86_CR4_UMIP_BIT) #define X86_CR4_LA57_BIT 12 /* enable 5-level page tables */ #define X86_CR4_LA57 _BITUL(X86_CR4_LA57_BIT) #define X86_CR4_VMXE_BIT 13 /* enable VMX virtualization */