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From: "tip-bot for Darrick J. Wong" <djwong@us.ibm.com>
To: linux-tip-commits@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, hpa@zytor.com, mingo@redhat.com,
	djwong@us.ibm.com, muli@il.ibm.com, cschultz@linux.vnet.ibm.com,
	stable@kernel.org, tglx@linutronix.de, mingo@elte.hu
Subject: [tip:x86/urgent] x86, Calgary: Increase max PHB number
Date: Fri, 25 Jun 2010 15:29:50 GMT	[thread overview]
Message-ID: <tip-499a00e92dd9a75395081f595e681629eb1eebad@git.kernel.org> (raw)
In-Reply-To: <20100624212647.GI15515@tux1.beaverton.ibm.com>

Commit-ID:  499a00e92dd9a75395081f595e681629eb1eebad
Gitweb:     http://git.kernel.org/tip/499a00e92dd9a75395081f595e681629eb1eebad
Author:     Darrick J. Wong <djwong@us.ibm.com>
AuthorDate: Thu, 24 Jun 2010 14:26:47 -0700
Committer:  Ingo Molnar <mingo@elte.hu>
CommitDate: Fri, 25 Jun 2010 16:14:58 +0200

x86, Calgary: Increase max PHB number

Newer systems (x3950M2) can have 48 PHBs per chassis and 8
chassis, so bump the limits up and provide an explanation
of the requirements for each class.

Signed-off-by: Darrick J. Wong <djwong@us.ibm.com>
Acked-by: Muli Ben-Yehuda <muli@il.ibm.com>
Cc: Corinna Schultz <cschultz@linux.vnet.ibm.com>
Cc: <stable@kernel.org>
LKML-Reference: <20100624212647.GI15515@tux1.beaverton.ibm.com>
[ v2: Fixed build bug, added back PHBS_PER_CALGARY == 4 ]
Signed-off-by: Ingo Molnar <mingo@elte.hu>
---
 arch/x86/kernel/pci-calgary_64.c |   15 ++++++++++-----
 1 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/arch/x86/kernel/pci-calgary_64.c b/arch/x86/kernel/pci-calgary_64.c
index fb99f7e..0b96b55 100644
--- a/arch/x86/kernel/pci-calgary_64.c
+++ b/arch/x86/kernel/pci-calgary_64.c
@@ -103,11 +103,16 @@ int use_calgary __read_mostly = 0;
 #define PMR_SOFTSTOPFAULT	0x40000000
 #define PMR_HARDSTOP		0x20000000
 
-#define MAX_NUM_OF_PHBS		8 /* how many PHBs in total? */
-#define MAX_NUM_CHASSIS		8 /* max number of chassis */
-/* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
-#define MAX_PHB_BUS_NUM		(MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2)
-#define PHBS_PER_CALGARY	4
+/*
+ * The maximum PHB bus number.
+ * x3950M2 (rare): 8 chassis, 48 PHBs per chassis = 384
+ * x3950M2: 4 chassis, 48 PHBs per chassis        = 192
+ * x3950 (PCIE): 8 chassis, 32 PHBs per chassis   = 256
+ * x3950 (PCIX): 8 chassis, 16 PHBs per chassis   = 128
+ */
+#define MAX_PHB_BUS_NUM		384
+
+#define PHBS_PER_CALGARY	  4
 
 /* register offsets in Calgary's internal register space */
 static const unsigned long tar_offsets[] = {

  parent reply	other threads:[~2010-06-25 15:30 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-06-21 18:41 [PATCH RESEND] (revised) Calgary: increase " Corinna Schultz
2010-06-24 21:26 ` Darrick J. Wong
2010-06-25 14:14   ` Ingo Molnar
2010-06-25 15:29   ` tip-bot for Darrick J. Wong [this message]
2010-06-29 22:51     ` [tip:x86/urgent] x86, Calgary: Increase " Andrew Morton
2010-06-30 21:31       ` H. Peter Anvin
2010-06-30 21:45         ` Darrick J. Wong
2010-06-30 21:49         ` [PATCH] " Darrick J. Wong
2010-06-30 23:05           ` H. Peter Anvin
2010-07-01  0:45             ` Darrick J. Wong
2010-07-01  5:45               ` [tip:x86/urgent] x86, Calgary: Limit the max PHB number to 256 tip-bot for Darrick J. Wong

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