From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754637AbbIOPtQ (ORCPT ); Tue, 15 Sep 2015 11:49:16 -0400 Received: from terminus.zytor.com ([198.137.202.10]:57166 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751923AbbIOPtN (ORCPT ); Tue, 15 Sep 2015 11:49:13 -0400 Date: Tue, 15 Sep 2015 08:48:53 -0700 From: tip-bot for Marc Zyngier Message-ID: Cc: stuart.yoder@freescale.com, tglx@linutronix.de, hpa@zytor.com, linux-kernel@vger.kernel.org, p.fedin@samsung.com, jason@lakedaemon.net, mingo@kernel.org, marc.zyngier@arm.com Reply-To: linux-kernel@vger.kernel.org, jason@lakedaemon.net, p.fedin@samsung.com, mingo@kernel.org, marc.zyngier@arm.com, tglx@linutronix.de, hpa@zytor.com, stuart.yoder@freescale.com In-Reply-To: <1442142873-20213-3-git-send-email-marc.zyngier@arm.com> References: <1442142873-20213-3-git-send-email-marc.zyngier@arm.com> To: linux-tip-commits@vger.kernel.org Subject: [tip:irq/urgent] irqchip/gic-v3-its: Add missing cache flushes Git-Commit-ID: 5a9a8915c8888b615521b17d70a4342187eae60b X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit-ID: 5a9a8915c8888b615521b17d70a4342187eae60b Gitweb: http://git.kernel.org/tip/5a9a8915c8888b615521b17d70a4342187eae60b Author: Marc Zyngier AuthorDate: Sun, 13 Sep 2015 12:14:32 +0100 Committer: Thomas Gleixner CommitDate: Tue, 15 Sep 2015 17:06:29 +0200 irqchip/gic-v3-its: Add missing cache flushes When the ITS is configured for non-cacheable transactions, make sure that the allocated, zeroed memory is flushed to the Point of Coherency, allowing the ITS to observe the zeros instead of random garbage (or even get its own data overwritten by zeros being evicted from the cache...). Fixes: 241a386c7dbb "irqchip: gicv3-its: Use non-cacheable accesses when no shareability" Reported-and-tested-by: Stuart Yoder Signed-off-by: Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org Cc: Pavel Fedin Cc: Jason Cooper Link: http://lkml.kernel.org/r/1442142873-20213-3-git-send-email-marc.zyngier@arm.com Signed-off-by: Thomas Gleixner --- drivers/irqchip/irq-gic-v3-its.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index 26b55c5..ac7ae2b 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -898,8 +898,10 @@ retry_baser: * non-cacheable as well. */ shr = tmp & GITS_BASER_SHAREABILITY_MASK; - if (!shr) + if (!shr) { cache = GITS_BASER_nC; + __flush_dcache_area(base, alloc_size); + } goto retry_baser; } @@ -1140,6 +1142,8 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id, return NULL; } + __flush_dcache_area(itt, sz); + dev->its = its; dev->itt = itt; dev->nr_ites = nr_ites;