From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757282AbcEEJuN (ORCPT ); Thu, 5 May 2016 05:50:13 -0400 Received: from terminus.zytor.com ([198.137.202.10]:44846 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756610AbcEEJuJ (ORCPT ); Thu, 5 May 2016 05:50:09 -0400 Date: Thu, 5 May 2016 02:48:47 -0700 From: tip-bot for Alexander Shishkin Message-ID: Cc: bp@alien8.de, alexander.shishkin@linux.intel.com, jolsa@redhat.com, hpa@zytor.com, tglx@linutronix.de, mathieu.poirier@linaro.org, eranian@google.com, torvalds@linux-foundation.org, linux-kernel@vger.kernel.org, acme@redhat.com, vincent.weaver@maine.edu, peterz@infradead.org, mingo@kernel.org, acme@infradead.org Reply-To: hpa@zytor.com, alexander.shishkin@linux.intel.com, jolsa@redhat.com, bp@alien8.de, tglx@linutronix.de, eranian@google.com, mathieu.poirier@linaro.org, torvalds@linux-foundation.org, acme@infradead.org, mingo@kernel.org, peterz@infradead.org, vincent.weaver@maine.edu, linux-kernel@vger.kernel.org, acme@redhat.com In-Reply-To: <87zisdvibe.fsf@ashishki-desk.ger.corp.intel.com> References: <87zisdvibe.fsf@ashishki-desk.ger.corp.intel.com> To: linux-tip-commits@vger.kernel.org Subject: [tip:perf/core] perf/x86/intel/pt: Export CPU frequency ratios needed by PT decoders Git-Commit-ID: 65c7e6f1c4810e9bce935520f44f6d2613cd1b40 X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit-ID: 65c7e6f1c4810e9bce935520f44f6d2613cd1b40 Gitweb: http://git.kernel.org/tip/65c7e6f1c4810e9bce935520f44f6d2613cd1b40 Author: Alexander Shishkin AuthorDate: Wed, 19 Aug 2015 17:02:10 +0300 Committer: Ingo Molnar CommitDate: Thu, 5 May 2016 10:16:28 +0200 perf/x86/intel/pt: Export CPU frequency ratios needed by PT decoders Intel PT decoders need access to various bits of timing related information to be able to correctly decode timing packets from a PT stream (MTC and CBR packets). This patch exports all the necessary bits as sysfs attributes for the sake of consistency: * max_nonturbo_ratio: ratio between the invariant TSC and base clock; * tsc_art_ratio: TSC to core crystal clock ratio (also available as CPUID.15H). Signed-off-by: Alexander Shishkin Signed-off-by: Peter Zijlstra (Intel) Cc: Arnaldo Carvalho de Melo Cc: Arnaldo Carvalho de Melo Cc: Borislav Petkov Cc: Jiri Olsa Cc: Linus Torvalds Cc: Mathieu Poirier Cc: Peter Zijlstra Cc: Stephane Eranian Cc: Thomas Gleixner Cc: Vince Weaver Cc: vince@deater.net Link: http://lkml.kernel.org/r/87zisdvibe.fsf@ashishki-desk.ger.corp.intel.com Signed-off-by: Ingo Molnar --- arch/x86/events/intel/pt.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++ arch/x86/events/intel/pt.h | 6 ++++++ 2 files changed, 60 insertions(+) diff --git a/arch/x86/events/intel/pt.c b/arch/x86/events/intel/pt.c index 2d1ce2c..c3a359c 100644 --- a/arch/x86/events/intel/pt.c +++ b/arch/x86/events/intel/pt.c @@ -127,9 +127,46 @@ static struct attribute_group pt_format_group = { .attrs = pt_formats_attr, }; +static ssize_t +pt_timing_attr_show(struct device *dev, struct device_attribute *attr, + char *page) +{ + struct perf_pmu_events_attr *pmu_attr = + container_of(attr, struct perf_pmu_events_attr, attr); + + switch (pmu_attr->id) { + case 0: + return sprintf(page, "%lu\n", pt_pmu.max_nonturbo_ratio); + case 1: + return sprintf(page, "%u:%u\n", + pt_pmu.tsc_art_num, + pt_pmu.tsc_art_den); + default: + break; + } + + return -EINVAL; +} + +PMU_EVENT_ATTR(max_nonturbo_ratio, timing_attr_max_nonturbo_ratio, 0, + pt_timing_attr_show); +PMU_EVENT_ATTR(tsc_art_ratio, timing_attr_tsc_art_ratio, 1, + pt_timing_attr_show); + +static struct attribute *pt_timing_attr[] = { + &timing_attr_max_nonturbo_ratio.attr.attr, + &timing_attr_tsc_art_ratio.attr.attr, + NULL, +}; + +static struct attribute_group pt_timing_group = { + .attrs = pt_timing_attr, +}; + static const struct attribute_group *pt_attr_groups[] = { &pt_cap_group, &pt_format_group, + &pt_timing_group, NULL, }; @@ -142,6 +179,23 @@ static int __init pt_pmu_hw_init(void) int ret; long i; + rdmsrl(MSR_PLATFORM_INFO, reg); + pt_pmu.max_nonturbo_ratio = (reg & 0xff00) >> 8; + + /* + * if available, read in TSC to core crystal clock ratio, + * otherwise, zero for numerator stands for "not enumerated" + * as per SDM + */ + if (boot_cpu_data.cpuid_level >= CPUID_TSC_LEAF) { + u32 eax, ebx, ecx, edx; + + cpuid(CPUID_TSC_LEAF, &eax, &ebx, &ecx, &edx); + + pt_pmu.tsc_art_num = ebx; + pt_pmu.tsc_art_den = eax; + } + if (boot_cpu_has(X86_FEATURE_VMX)) { /* * Intel SDM, 36.5 "Tracing post-VMXON" says that diff --git a/arch/x86/events/intel/pt.h b/arch/x86/events/intel/pt.h index ca64599..efffa4a 100644 --- a/arch/x86/events/intel/pt.h +++ b/arch/x86/events/intel/pt.h @@ -82,6 +82,9 @@ struct topa_entry { #define PT_CPUID_LEAVES 2 #define PT_CPUID_REGS_NUM 4 /* number of regsters (eax, ebx, ecx, edx) */ +/* TSC to Core Crystal Clock Ratio */ +#define CPUID_TSC_LEAF 0x15 + enum pt_capabilities { PT_CAP_max_subleaf = 0, PT_CAP_cr3_filtering, @@ -102,6 +105,9 @@ struct pt_pmu { struct pmu pmu; u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES]; bool vmx; + unsigned long max_nonturbo_ratio; + unsigned int tsc_art_num; + unsigned int tsc_art_den; }; /**