From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752842AbcAFSxY (ORCPT ); Wed, 6 Jan 2016 13:53:24 -0500 Received: from terminus.zytor.com ([198.137.202.10]:54833 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751761AbcAFSxV (ORCPT ); Wed, 6 Jan 2016 13:53:21 -0500 Date: Wed, 6 Jan 2016 10:52:42 -0800 From: tip-bot for Stephane Eranian Message-ID: Cc: acme@redhat.com, hpa@zytor.com, vincent.weaver@maine.edu, peterz@infradead.org, mingo@kernel.org, tglx@linutronix.de, torvalds@linux-foundation.org, jolsa@redhat.com, linux-kernel@vger.kernel.org, eranian@google.com Reply-To: eranian@google.com, linux-kernel@vger.kernel.org, jolsa@redhat.com, torvalds@linux-foundation.org, mingo@kernel.org, tglx@linutronix.de, peterz@infradead.org, vincent.weaver@maine.edu, acme@redhat.com, hpa@zytor.com In-Reply-To: <1449172990-30183-3-git-send-email-eranian@google.com> References: <1449172990-30183-3-git-send-email-eranian@google.com> To: linux-tip-commits@vger.kernel.org Subject: [tip:perf/core] perf/x86: Enable cycles:pp for Intel Atom Git-Commit-ID: 673d188ba5b1cef6f9a41a5a18b490b2831c3ea5 X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit-ID: 673d188ba5b1cef6f9a41a5a18b490b2831c3ea5 Gitweb: http://git.kernel.org/tip/673d188ba5b1cef6f9a41a5a18b490b2831c3ea5 Author: Stephane Eranian AuthorDate: Thu, 3 Dec 2015 21:03:10 +0100 Committer: Ingo Molnar CommitDate: Wed, 6 Jan 2016 11:15:34 +0100 perf/x86: Enable cycles:pp for Intel Atom This patch updates the PEBS support for Intel Atom to provide an alias for the cycles:pp event used by perf record/top by default nowadays. On Atom, only INST_RETIRED:ANY supports PEBS, so we use this event instead with a large cmask to count cycles. Given that Core2 has the same issue, we use the intel_pebs_aliases_core2() function for Atom as well. Signed-off-by: Stephane Eranian Signed-off-by: Peter Zijlstra (Intel) Cc: Arnaldo Carvalho de Melo Cc: Jiri Olsa Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: Vince Weaver Cc: kan.liang@intel.com Link: http://lkml.kernel.org/r/1449172990-30183-3-git-send-email-eranian@google.com Signed-off-by: Ingo Molnar --- arch/x86/kernel/cpu/perf_event_intel.c | 1 + arch/x86/kernel/cpu/perf_event_intel_ds.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c index 762c602..95980c0 100644 --- a/arch/x86/kernel/cpu/perf_event_intel.c +++ b/arch/x86/kernel/cpu/perf_event_intel.c @@ -3370,6 +3370,7 @@ __init int intel_pmu_init(void) x86_pmu.event_constraints = intel_gen_event_constraints; x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints; + x86_pmu.pebs_aliases = intel_pebs_aliases_core2; pr_cont("Atom events, "); break; diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c b/arch/x86/kernel/cpu/perf_event_intel_ds.c index a7463ed..10602f0 100644 --- a/arch/x86/kernel/cpu/perf_event_intel_ds.c +++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c @@ -620,6 +620,8 @@ struct event_constraint intel_atom_pebs_event_constraints[] = { INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */ /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */ INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01), + /* Allow all events as PEBS with no flags */ + INTEL_ALL_EVENT_CONSTRAINT(0, 0x1), EVENT_CONSTRAINT_END };