From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755093AbdC3Ikn (ORCPT ); Thu, 30 Mar 2017 04:40:43 -0400 Received: from terminus.zytor.com ([65.50.211.136]:51279 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754897AbdC3Ikk (ORCPT ); Thu, 30 Mar 2017 04:40:40 -0400 Date: Thu, 30 Mar 2017 01:34:48 -0700 From: tip-bot for Suravee Suthikulpanit Message-ID: Cc: eranian@google.com, joro@8bytes.org, linux-kernel@vger.kernel.org, tglx@linutronix.de, hpa@zytor.com, suravee.suthikulpanit@amd.com, vincent.weaver@maine.edu, torvalds@linux-foundation.org, peterz@infradead.org, jolsa@redhat.com, mingo@kernel.org, acme@redhat.com, bp@suse.de, alexander.shishkin@linux.intel.com Reply-To: vincent.weaver@maine.edu, suravee.suthikulpanit@amd.com, tglx@linutronix.de, linux-kernel@vger.kernel.org, hpa@zytor.com, alexander.shishkin@linux.intel.com, mingo@kernel.org, bp@suse.de, acme@redhat.com, jolsa@redhat.com, peterz@infradead.org, torvalds@linux-foundation.org, joro@8bytes.org, eranian@google.com In-Reply-To: <1487926102-13073-3-git-send-email-Suravee.Suthikulpanit@amd.com> References: <1487926102-13073-3-git-send-email-Suravee.Suthikulpanit@amd.com> To: linux-tip-commits@vger.kernel.org Subject: [tip:perf/core] x86/events/amd/iommu: Clean up bitwise operations Git-Commit-ID: 6aad0c6269052a6114259deaf664ce350bf64fa2 X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit-ID: 6aad0c6269052a6114259deaf664ce350bf64fa2 Gitweb: http://git.kernel.org/tip/6aad0c6269052a6114259deaf664ce350bf64fa2 Author: Suravee Suthikulpanit AuthorDate: Fri, 24 Feb 2017 02:48:14 -0600 Committer: Ingo Molnar CommitDate: Thu, 30 Mar 2017 09:53:51 +0200 x86/events/amd/iommu: Clean up bitwise operations Clean up register initialization and make use of BIT_ULL(x) where appropriate. This should not affect logic and functionality. Signed-off-by: Suravee Suthikulpanit Signed-off-by: Borislav Petkov Signed-off-by: Peter Zijlstra (Intel) Cc: Alexander Shishkin Cc: Arnaldo Carvalho de Melo Cc: Jiri Olsa Cc: Jörg Rödel Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Stephane Eranian Cc: Thomas Gleixner Cc: Vince Weaver Cc: iommu@lists.linux-foundation.org Link: http://lkml.kernel.org/r/1487926102-13073-3-git-send-email-Suravee.Suthikulpanit@amd.com Signed-off-by: Ingo Molnar --- arch/x86/events/amd/iommu.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/x86/events/amd/iommu.c b/arch/x86/events/amd/iommu.c index 8d8ed40..e112f49 100644 --- a/arch/x86/events/amd/iommu.c +++ b/arch/x86/events/amd/iommu.c @@ -164,11 +164,11 @@ static int get_next_avail_iommu_bnk_cntr(struct perf_amd_iommu *perf_iommu) for (bank = 0, shift = 0; bank < max_banks; bank++) { for (cntr = 0; cntr < max_cntrs; cntr++) { shift = bank + (bank*3) + cntr; - if (perf_iommu->cntr_assign_mask & (1ULL<cntr_assign_mask & BIT_ULL(shift)) { continue; } else { - perf_iommu->cntr_assign_mask |= (1ULL<cntr_assign_mask |= BIT_ULL(shift); + retval = ((bank & 0xFF) << 8) | (cntr & 0xFF); goto out; } } @@ -265,23 +265,23 @@ static void perf_iommu_enable_event(struct perf_event *ev) _GET_BANK(ev), _GET_CNTR(ev) , IOMMU_PC_COUNTER_SRC_REG, ®, true); - reg = 0ULL | devid | (_GET_DEVID_MASK(ev) << 32); + reg = devid | (_GET_DEVID_MASK(ev) << 32); if (reg) - reg |= (1UL << 31); + reg |= BIT(31); amd_iommu_pc_get_set_reg_val(devid, _GET_BANK(ev), _GET_CNTR(ev) , IOMMU_PC_DEVID_MATCH_REG, ®, true); - reg = 0ULL | _GET_PASID(ev) | (_GET_PASID_MASK(ev) << 32); + reg = _GET_PASID(ev) | (_GET_PASID_MASK(ev) << 32); if (reg) - reg |= (1UL << 31); + reg |= BIT(31); amd_iommu_pc_get_set_reg_val(devid, _GET_BANK(ev), _GET_CNTR(ev) , IOMMU_PC_PASID_MATCH_REG, ®, true); - reg = 0ULL | _GET_DOMID(ev) | (_GET_DOMID_MASK(ev) << 32); + reg = _GET_DOMID(ev) | (_GET_DOMID_MASK(ev) << 32); if (reg) - reg |= (1UL << 31); + reg |= BIT(31); amd_iommu_pc_get_set_reg_val(devid, _GET_BANK(ev), _GET_CNTR(ev) , IOMMU_PC_DOMID_MATCH_REG, ®, true);