From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757676AbdJPVTm (ORCPT ); Mon, 16 Oct 2017 17:19:42 -0400 Received: from terminus.zytor.com ([65.50.211.136]:41877 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757664AbdJPVTk (ORCPT ); Mon, 16 Oct 2017 17:19:40 -0400 Date: Mon, 16 Oct 2017 14:17:10 -0700 From: "tip-bot for mike.travis@hpe.com" Message-ID: Cc: linux-kernel@vger.kernel.org, russ.anderson@hpe.com, mike.travis@hpe.com, peterz@infradead.org, prarit@redhat.com, hpa@zytor.com, dimitri.sivanich@hpe.com, mingo@kernel.org, andrew.banman@hpe.com, bin.gao@linux.intel.com, tglx@linutronix.de Reply-To: linux-kernel@vger.kernel.org, russ.anderson@hpe.com, mike.travis@hpe.com, prarit@redhat.com, peterz@infradead.org, hpa@zytor.com, mingo@kernel.org, dimitri.sivanich@hpe.com, andrew.banman@hpe.com, bin.gao@linux.intel.com, tglx@linutronix.de In-Reply-To: <20171012163202.289397994@stormcage.americas.sgi.com> References: <20171012163202.289397994@stormcage.americas.sgi.com> To: linux-tip-commits@vger.kernel.org Subject: [tip:x86/timers] x86/tsc: Provide a means to disable TSC ART Git-Commit-ID: 6c66350d0a482892793b888b07c1177fc6d4b344 X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit-ID: 6c66350d0a482892793b888b07c1177fc6d4b344 Gitweb: https://git.kernel.org/tip/6c66350d0a482892793b888b07c1177fc6d4b344 Author: mike.travis@hpe.com AuthorDate: Thu, 12 Oct 2017 11:32:05 -0500 Committer: Thomas Gleixner CommitDate: Mon, 16 Oct 2017 22:50:37 +0200 x86/tsc: Provide a means to disable TSC ART On systems where multiple chassis are reset asynchronously, and thus the TSC counters are started asynchronously, the offset needed to convert to TSC to ART would be different. Disable ART in that case and rely on the TSC counters to supply the accurate time. Signed-off-by: Mike Travis Signed-off-by: Thomas Gleixner Reviewed-by: Thomas Gleixner Cc: Prarit Bhargava Cc: Dimitri Sivanich Cc: Russ Anderson Cc: Andrew Banman Cc: Peter Zijlstra Cc: Bin Gao Link: https://lkml.kernel.org/r/20171012163202.289397994@stormcage.americas.sgi.com --- arch/x86/kernel/tsc.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index 896dbe3..f1326c0 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -962,10 +962,14 @@ static void detect_art(void) if (boot_cpu_data.cpuid_level < ART_CPUID_LEAF) return; - /* Don't enable ART in a VM, non-stop TSC and TSC_ADJUST required */ + /* + * Don't enable ART in a VM, non-stop TSC and TSC_ADJUST required, + * and the TSC counter resets must not occur asynchronously. + */ if (boot_cpu_has(X86_FEATURE_HYPERVISOR) || !boot_cpu_has(X86_FEATURE_NONSTOP_TSC) || - !boot_cpu_has(X86_FEATURE_TSC_ADJUST)) + !boot_cpu_has(X86_FEATURE_TSC_ADJUST) || + tsc_async_resets) return; cpuid(ART_CPUID_LEAF, &art_to_tsc_denominator,