From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752739AbcAFSwt (ORCPT ); Wed, 6 Jan 2016 13:52:49 -0500 Received: from terminus.zytor.com ([198.137.202.10]:54805 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752256AbcAFSwo (ORCPT ); Wed, 6 Jan 2016 13:52:44 -0500 Date: Wed, 6 Jan 2016 10:52:05 -0800 From: tip-bot for Stephane Eranian Message-ID: Cc: hpa@zytor.com, mingo@kernel.org, jolsa@redhat.com, linux-kernel@vger.kernel.org, torvalds@linux-foundation.org, vincent.weaver@maine.edu, tglx@linutronix.de, peterz@infradead.org, eranian@google.com, acme@redhat.com Reply-To: hpa@zytor.com, mingo@kernel.org, jolsa@redhat.com, linux-kernel@vger.kernel.org, torvalds@linux-foundation.org, vincent.weaver@maine.edu, tglx@linutronix.de, peterz@infradead.org, eranian@google.com, acme@redhat.com In-Reply-To: <1449182000-31524-2-git-send-email-eranian@google.com> References: <1449182000-31524-2-git-send-email-eranian@google.com> To: linux-tip-commits@vger.kernel.org Subject: [tip:perf/core] perf/x86: Fix LBR related crashes on Intel Atom Git-Commit-ID: 6fc2e83077b05a061afe9b24f2fdff7a0434eb67 X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit-ID: 6fc2e83077b05a061afe9b24f2fdff7a0434eb67 Gitweb: http://git.kernel.org/tip/6fc2e83077b05a061afe9b24f2fdff7a0434eb67 Author: Stephane Eranian AuthorDate: Thu, 3 Dec 2015 23:33:17 +0100 Committer: Ingo Molnar CommitDate: Wed, 6 Jan 2016 11:15:33 +0100 perf/x86: Fix LBR related crashes on Intel Atom This patches fixes the LBR kernel crashes on Intel Atom. The kernel was assuming that if the CPU supports 64-bit format LBR, then it has an LBR_SELECT MSR. Atom uses 64-bit LBR format but does not have LBR_SELECT. That was causing NULL pointer dereferences in a couple of places. Signed-off-by: Stephane Eranian Signed-off-by: Peter Zijlstra (Intel) Cc: Arnaldo Carvalho de Melo Cc: Jiri Olsa Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: Vince Weaver Cc: kan.liang@intel.com Fixes: 96f3eda67fcf ("perf/x86/intel: Fix static checker warning in lbr enable") Link: http://lkml.kernel.org/r/1449182000-31524-2-git-send-email-eranian@google.com Signed-off-by: Ingo Molnar --- arch/x86/kernel/cpu/perf_event_intel_lbr.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/arch/x86/kernel/cpu/perf_event_intel_lbr.c index e2fad0c..1390148 100644 --- a/arch/x86/kernel/cpu/perf_event_intel_lbr.c +++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c @@ -161,7 +161,7 @@ static void __intel_pmu_lbr_enable(bool pmi) */ if (cpuc->lbr_sel) lbr_select = cpuc->lbr_sel->config & x86_pmu.lbr_sel_mask; - if (!pmi) + if (!pmi && cpuc->lbr_sel) wrmsrl(MSR_LBR_SELECT, lbr_select); rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); @@ -430,7 +430,7 @@ static void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc) */ static void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc) { - bool need_info = !(cpuc->lbr_sel->config & LBR_NO_INFO); + bool need_info = false; unsigned long mask = x86_pmu.lbr_nr - 1; int lbr_format = x86_pmu.intel_cap.lbr_format; u64 tos = intel_pmu_lbr_tos(); @@ -438,8 +438,11 @@ static void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc) int out = 0; int num = x86_pmu.lbr_nr; - if (cpuc->lbr_sel->config & LBR_CALL_STACK) - num = tos; + if (cpuc->lbr_sel) { + need_info = !(cpuc->lbr_sel->config & LBR_NO_INFO); + if (cpuc->lbr_sel->config & LBR_CALL_STACK) + num = tos; + } for (i = 0; i < num; i++) { unsigned long lbr_idx = (tos - i) & mask;