From: tip-bot for Reinette Chatre <tipbot@zytor.com>
To: linux-tip-commits@vger.kernel.org
Cc: reinette.chatre@intel.com, linux-kernel@vger.kernel.org,
hpa@zytor.com, mingo@kernel.org, mingo@redhat.com,
fenghua.yu@intel.com, tony.luck@intel.com, tglx@linutronix.de,
x86@kernel.org, bp@suse.de
Subject: [tip:x86/cleanups] x86/resctrl: Remove duplicate MSR_MISC_FEATURE_CONTROL definition
Date: Mon, 4 Feb 2019 22:28:05 -0800 [thread overview]
Message-ID: <tip-8ad382dd11ebed9f87edfeda6e738c472a911203@git.kernel.org> (raw)
In-Reply-To: <ff6b95d9b6ef6f4ac96267f130719ba1af09614b.1549312475.git.reinette.chatre@intel.com>
Commit-ID: 8ad382dd11ebed9f87edfeda6e738c472a911203
Gitweb: https://git.kernel.org/tip/8ad382dd11ebed9f87edfeda6e738c472a911203
Author: Reinette Chatre <reinette.chatre@intel.com>
AuthorDate: Mon, 4 Feb 2019 12:41:36 -0800
Committer: Borislav Petkov <bp@suse.de>
CommitDate: Tue, 5 Feb 2019 07:21:56 +0100
x86/resctrl: Remove duplicate MSR_MISC_FEATURE_CONTROL definition
The definition of MSR_MISC_FEATURE_CONTROL was first introduced in
98af74599ea0 ("x86 msr_index.h: Define MSR_MISC_FEATURE_CONTROL")
and present in Linux since v4.11.
The Cache Pseudo-Locking code added this duplicate definition in more
recent
f2a177292bd0 ("x86/intel_rdt: Discover supported platforms via prefetch disable bits"),
available since v4.19.
Remove the duplicate definition from the resctrl subsystem and let that
code obtain the needed definition from the core architecture msr-index.h
instead.
Fixes: f2a177292bd0 ("x86/intel_rdt: Discover supported platforms via prefetch disable bits")
Signed-off-by: Reinette Chatre <reinette.chatre@intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Fenghua Yu <fenghua.yu@intel.com>
Cc: gavin.hindman@intel.com
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: jithu.joseph@intel.com
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: x86-ml <x86@kernel.org>
Link: https://lkml.kernel.org/r/ff6b95d9b6ef6f4ac96267f130719ba1af09614b.1549312475.git.reinette.chatre@intel.com
---
arch/x86/kernel/cpu/resctrl/pseudo_lock.c | 7 -------
1 file changed, 7 deletions(-)
diff --git a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c
index 14bed6af8377..604c0e3bcc83 100644
--- a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c
+++ b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c
@@ -33,13 +33,6 @@
#define CREATE_TRACE_POINTS
#include "pseudo_lock_event.h"
-/*
- * MSR_MISC_FEATURE_CONTROL register enables the modification of hardware
- * prefetcher state. Details about this register can be found in the MSR
- * tables for specific platforms found in Intel's SDM.
- */
-#define MSR_MISC_FEATURE_CONTROL 0x000001a4
-
/*
* The bits needed to disable hardware prefetching varies based on the
* platform. During initialization we will discover which bits to use.
prev parent reply other threads:[~2019-02-05 6:28 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-04 20:41 [PATCH] " Reinette Chatre
2019-02-05 6:28 ` tip-bot for Reinette Chatre [this message]
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