From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752358AbdHJMHH (ORCPT ); Thu, 10 Aug 2017 08:07:07 -0400 Received: from terminus.zytor.com ([65.50.211.136]:33723 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751998AbdHJMHD (ORCPT ); Thu, 10 Aug 2017 08:07:03 -0400 Date: Thu, 10 Aug 2017 05:02:33 -0700 From: tip-bot for Janakarajan Natarajan Message-ID: Cc: peterz@infradead.org, hpa@zytor.com, alexander.shishkin@linux.intel.com, Janakarajan.Natarajan@amd.com, tglx@linutronix.de, torvalds@linux-foundation.org, mingo@kernel.org, linux-kernel@vger.kernel.org, suravee.suthikulpanit@amd.com, acme@kernel.org, bp@suse.de Reply-To: acme@kernel.org, bp@suse.de, suravee.suthikulpanit@amd.com, linux-kernel@vger.kernel.org, torvalds@linux-foundation.org, tglx@linutronix.de, mingo@kernel.org, alexander.shishkin@linux.intel.com, Janakarajan.Natarajan@amd.com, hpa@zytor.com, peterz@infradead.org In-Reply-To: <016311029fdecdc3fdc13b7ed865c6cbf48b2f15.1497452002.git.Janakarajan.Natarajan@amd.com> References: <016311029fdecdc3fdc13b7ed865c6cbf48b2f15.1497452002.git.Janakarajan.Natarajan@amd.com> To: linux-tip-commits@vger.kernel.org Subject: [tip:perf/core] perf/x86/amd/uncore: Rename cpufeatures macro for cache counters Git-Commit-ID: 910448bbed066ab1082b510eef1ae61bb792d854 X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit-ID: 910448bbed066ab1082b510eef1ae61bb792d854 Gitweb: http://git.kernel.org/tip/910448bbed066ab1082b510eef1ae61bb792d854 Author: Janakarajan Natarajan AuthorDate: Wed, 14 Jun 2017 11:26:57 -0500 Committer: Ingo Molnar CommitDate: Thu, 10 Aug 2017 12:08:38 +0200 perf/x86/amd/uncore: Rename cpufeatures macro for cache counters In Family 17h, L3 is the last level cache as opposed to L2 in previous families. Avoid this name confusion and rename X86_FEATURE_PERFCTR_L2 to X86_FEATURE_PERFCTR_LLC to indicate the performance counter on the last level of cache. Signed-off-by: Janakarajan Natarajan Signed-off-by: Peter Zijlstra (Intel) Reviewed-by: Borislav Petkov Cc: Alexander Shishkin Cc: Arnaldo Carvalho de Melo Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Suravee Suthikulpanit Cc: Thomas Gleixner Link: http://lkml.kernel.org/r/016311029fdecdc3fdc13b7ed865c6cbf48b2f15.1497452002.git.Janakarajan.Natarajan@amd.com Signed-off-by: Ingo Molnar --- arch/x86/events/amd/uncore.c | 2 +- arch/x86/include/asm/cpufeatures.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c index ad44af0..e34f8a6 100644 --- a/arch/x86/events/amd/uncore.c +++ b/arch/x86/events/amd/uncore.c @@ -555,7 +555,7 @@ static int __init amd_uncore_init(void) ret = 0; } - if (boot_cpu_has(X86_FEATURE_PERFCTR_L2)) { + if (boot_cpu_has(X86_FEATURE_PERFCTR_LLC)) { amd_uncore_llc = alloc_percpu(struct amd_uncore *); if (!amd_uncore_llc) { ret = -ENOMEM; diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index ca3c48c..73a7127 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -177,7 +177,7 @@ #define X86_FEATURE_PERFCTR_NB ( 6*32+24) /* NB performance counter extensions */ #define X86_FEATURE_BPEXT (6*32+26) /* data breakpoint extension */ #define X86_FEATURE_PTSC ( 6*32+27) /* performance time-stamp counter */ -#define X86_FEATURE_PERFCTR_L2 ( 6*32+28) /* L2 performance counter extensions */ +#define X86_FEATURE_PERFCTR_LLC ( 6*32+28) /* Last Level Cache performance counter extensions */ #define X86_FEATURE_MWAITX ( 6*32+29) /* MWAIT extension (MONITORX/MWAITX) */ /*