From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933560AbeAXLa2 (ORCPT ); Wed, 24 Jan 2018 06:30:28 -0500 Received: from terminus.zytor.com ([65.50.211.136]:43479 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933129AbeAXLaZ (ORCPT ); Wed, 24 Jan 2018 06:30:25 -0500 Date: Wed, 24 Jan 2018 03:29:18 -0800 From: tip-bot for Andi Kleen Message-ID: Cc: ak@linux.intel.com, tglx@linutronix.de, linux-kernel@vger.kernel.org, hpa@zytor.com, mingo@kernel.org Reply-To: mingo@kernel.org, hpa@zytor.com, tglx@linutronix.de, linux-kernel@vger.kernel.org, ak@linux.intel.com In-Reply-To: <20180118234518.GA27753@tassilo.jf.intel.com> References: <20180118234518.GA27753@tassilo.jf.intel.com> To: linux-tip-commits@vger.kernel.org Subject: [tip:perf/core] perf vendor events intel: Update Silvermont events to V14 Git-Commit-ID: 9500cc82d47eb662b609fa9a0480b5d0814b0bed X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit-ID: 9500cc82d47eb662b609fa9a0480b5d0814b0bed Gitweb: https://git.kernel.org/tip/9500cc82d47eb662b609fa9a0480b5d0814b0bed Author: Andi Kleen AuthorDate: Thu, 18 Jan 2018 04:52:48 -0800 Committer: Arnaldo Carvalho de Melo CommitDate: Tue, 23 Jan 2018 09:51:42 -0300 perf vendor events intel: Update Silvermont events to V14 Link: https://lkml.kernel.org/r/20180118234518.GA27753@tassilo.jf.intel.com Signed-off-by: Andi Kleen --- tools/perf/pmu-events/arch/x86/silvermont/cache.json | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tools/perf/pmu-events/arch/x86/silvermont/cache.json b/tools/perf/pmu-events/arch/x86/silvermont/cache.json index 0bd1bc5..82be7d1 100644 --- a/tools/perf/pmu-events/arch/x86/silvermont/cache.json +++ b/tools/perf/pmu-events/arch/x86/silvermont/cache.json @@ -36,12 +36,13 @@ "BriefDescription": "L2 cache request misses" }, { + "PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ICache miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ICache miss. Note: this event is not the same as the total number of cycles spent retrieving instruction cache lines from the memory hierarchy.\r\nCounts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes. This will include cycles due to an ITLB miss, ICache miss and other events. \r\n", "EventCode": "0x86", "Counter": "0,1", "UMask": "0x4", "EventName": "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of cycles the NIP stalls because of an icache miss. This is a cumulative count of cycles the NIP stalled for all icache misses." + "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss." }, { "PEBS": "1",