From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965869AbcCJLGQ (ORCPT ); Thu, 10 Mar 2016 06:06:16 -0500 Received: from torg.zytor.com ([198.137.202.12]:38286 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S965742AbcCJLGG (ORCPT ); Thu, 10 Mar 2016 06:06:06 -0500 Date: Thu, 10 Mar 2016 03:05:26 -0800 From: tip-bot for Yu-cheng Yu Message-ID: Cc: sai.praneeth.prakhya@intel.com, leonid.shatz@ravellosystems.com, yu-cheng.yu@intel.com, luto@kernel.org, tglx@linutronix.de, linux-kernel@vger.kernel.org, ravi.v.shankar@intel.com, dave.hansen@linux.intel.com, hpa@zytor.com, mingo@kernel.org, bp@suse.de, fenghua.yu@intel.com, torvalds@linux-foundation.org, peterz@infradead.org Reply-To: mingo@kernel.org, hpa@zytor.com, dave.hansen@linux.intel.com, peterz@infradead.org, torvalds@linux-foundation.org, fenghua.yu@intel.com, bp@suse.de, luto@kernel.org, yu-cheng.yu@intel.com, leonid.shatz@ravellosystems.com, ravi.v.shankar@intel.com, tglx@linutronix.de, linux-kernel@vger.kernel.org, sai.praneeth.prakhya@intel.com In-Reply-To: <1457569734-3785-1-git-send-email-yu-cheng.yu@intel.com> References: <1457569734-3785-1-git-send-email-yu-cheng.yu@intel.com> To: linux-tip-commits@vger.kernel.org Subject: [tip:x86/urgent] x86/fpu: Revert ("x86/fpu: Disable AVX when eagerfpu is off") Git-Commit-ID: a65050c6f17e52442716138d48d0a47301a8344b X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit-ID: a65050c6f17e52442716138d48d0a47301a8344b Gitweb: http://git.kernel.org/tip/a65050c6f17e52442716138d48d0a47301a8344b Author: Yu-cheng Yu AuthorDate: Wed, 9 Mar 2016 16:28:54 -0800 Committer: Ingo Molnar CommitDate: Thu, 10 Mar 2016 10:15:58 +0100 x86/fpu: Revert ("x86/fpu: Disable AVX when eagerfpu is off") Leonid Shatz noticed that the SDM interpretation of the following recent commit: 394db20ca240741 ("x86/fpu: Disable AVX when eagerfpu is off") ... is incorrect and that the original behavior of the FPU code was correct. Because AVX is not stated in CR0 TS bit description, it was mistakenly believed to be not supported for lazy context switch. This turns out to be false: Intel Software Developer's Manual Vol. 3A, Sec. 2.5 Control Registers: 'TS Task Switched bit (bit 3 of CR0) -- Allows the saving of the x87 FPU/ MMX/SSE/SSE2/SSE3/SSSE3/SSE4 context on a task switch to be delayed until an x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instruction is actually executed by the new task.' Intel Software Developer's Manual Vol. 2A, Sec. 2.4 Instruction Exception Specification: 'AVX instructions refer to exceptions by classes that include #NM "Device Not Available" exception for lazy context switch.' So revert the commit. Reported-by: Leonid Shatz Signed-off-by: Yu-cheng Yu Cc: Andy Lutomirski Cc: Borislav Petkov Cc: Dave Hansen Cc: Fenghua Yu Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Ravi V. Shankar Cc: Sai Praneeth Prakhya Cc: Thomas Gleixner Link: http://lkml.kernel.org/r/1457569734-3785-1-git-send-email-yu-cheng.yu@intel.com Signed-off-by: Ingo Molnar --- arch/x86/include/asm/fpu/xstate.h | 9 ++++----- arch/x86/kernel/fpu/init.c | 6 ------ 2 files changed, 4 insertions(+), 11 deletions(-) diff --git a/arch/x86/include/asm/fpu/xstate.h b/arch/x86/include/asm/fpu/xstate.h index af30fde..f23cd8c 100644 --- a/arch/x86/include/asm/fpu/xstate.h +++ b/arch/x86/include/asm/fpu/xstate.h @@ -20,16 +20,15 @@ /* Supported features which support lazy state saving */ #define XFEATURE_MASK_LAZY (XFEATURE_MASK_FP | \ - XFEATURE_MASK_SSE) - -/* Supported features which require eager state saving */ -#define XFEATURE_MASK_EAGER (XFEATURE_MASK_BNDREGS | \ - XFEATURE_MASK_BNDCSR | \ + XFEATURE_MASK_SSE | \ XFEATURE_MASK_YMM | \ XFEATURE_MASK_OPMASK | \ XFEATURE_MASK_ZMM_Hi256 | \ XFEATURE_MASK_Hi16_ZMM) +/* Supported features which require eager state saving */ +#define XFEATURE_MASK_EAGER (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR) + /* All currently supported features */ #define XCNTXT_MASK (XFEATURE_MASK_LAZY | XFEATURE_MASK_EAGER) diff --git a/arch/x86/kernel/fpu/init.c b/arch/x86/kernel/fpu/init.c index d53ab3d..9ee7e30 100644 --- a/arch/x86/kernel/fpu/init.c +++ b/arch/x86/kernel/fpu/init.c @@ -302,12 +302,6 @@ u64 __init fpu__get_supported_xfeatures_mask(void) static void __init fpu__clear_eager_fpu_features(void) { setup_clear_cpu_cap(X86_FEATURE_MPX); - setup_clear_cpu_cap(X86_FEATURE_AVX); - setup_clear_cpu_cap(X86_FEATURE_AVX2); - setup_clear_cpu_cap(X86_FEATURE_AVX512F); - setup_clear_cpu_cap(X86_FEATURE_AVX512PF); - setup_clear_cpu_cap(X86_FEATURE_AVX512ER); - setup_clear_cpu_cap(X86_FEATURE_AVX512CD); } /*