From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751414AbdBDQbC (ORCPT ); Sat, 4 Feb 2017 11:31:02 -0500 Received: from terminus.zytor.com ([65.50.211.136]:57072 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751350AbdBDQbA (ORCPT ); Sat, 4 Feb 2017 11:31:00 -0500 Date: Sat, 4 Feb 2017 08:30:51 -0800 From: tip-bot for Grzegorz Andrejczuk Message-ID: Cc: grzegorz.andrejczuk@intel.com, mingo@kernel.org, linux-kernel@vger.kernel.org, tglx@linutronix.de, hpa@zytor.com Reply-To: hpa@zytor.com, tglx@linutronix.de, linux-kernel@vger.kernel.org, mingo@kernel.org, grzegorz.andrejczuk@intel.com In-Reply-To: <1484918557-15481-2-git-send-email-grzegorz.andrejczuk@intel.com> References: <1484918557-15481-2-git-send-email-grzegorz.andrejczuk@intel.com> To: linux-tip-commits@vger.kernel.org Subject: [tip:x86/cpufeature] x86/msr: Add MSR_MISC_FEATURE_ENABLES and RING3MWAIT bit Git-Commit-ID: ae47eda905e61ef6ba0b6f79b967c9de15ca4f8e X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit-ID: ae47eda905e61ef6ba0b6f79b967c9de15ca4f8e Gitweb: http://git.kernel.org/tip/ae47eda905e61ef6ba0b6f79b967c9de15ca4f8e Author: Grzegorz Andrejczuk AuthorDate: Fri, 20 Jan 2017 14:22:33 +0100 Committer: Thomas Gleixner CommitDate: Sat, 4 Feb 2017 08:51:09 +0100 x86/msr: Add MSR_MISC_FEATURE_ENABLES and RING3MWAIT bit Define new MSR MISC_FEATURE_ENABLES (0x140). On supported CPUs if bit 1 of this MSR is set, then calling MONITOR and MWAIT instructions outside of ring 0 will not cause invalid-opcode exception. The MSR MISC_FEATURE_ENABLES is not yet documented in the SDM. Here is the relevant documentation: Hex Dec Name Scope 140H 320 MISC_FEATURE_ENABLES Thread 0 Reserved 1 If set to 1, the MONITOR and MWAIT instructions do not cause invalid-opcode exceptions when executed with CPL > 0 or in virtual-8086 mode. If MWAIT is executed when CPL > 0 or in virtual-8086 mode, and if EAX indicates a C-state other than C0 or C1, the instruction operates as if EAX indicated the C-state C1. 63:2 Reserved Signed-off-by: Grzegorz Andrejczuk Cc: Piotr.Luc@intel.com Cc: dave.hansen@linux.intel.com Link: http://lkml.kernel.org/r/1484918557-15481-2-git-send-email-grzegorz.andrejczuk@intel.com Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/msr-index.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 710273c..00293a9 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -543,6 +543,11 @@ #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT) +/* MISC_FEATURE_ENABLES non-architectural features */ +#define MSR_MISC_FEATURE_ENABLES 0x00000140 + +#define MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT 1 + #define MSR_IA32_TSC_DEADLINE 0x000006E0 /* P4/Xeon+ specific */