From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753898AbcLLGxU (ORCPT ); Mon, 12 Dec 2016 01:53:20 -0500 Received: from terminus.zytor.com ([198.137.202.10]:49632 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750780AbcLLGxS (ORCPT ); Mon, 12 Dec 2016 01:53:18 -0500 Date: Sun, 11 Dec 2016 22:49:13 -0800 From: tip-bot for Andi Kleen Message-ID: Cc: linux-kernel@vger.kernel.org, ak@linux.intel.com, tglx@linutronix.de, stable@vger.kernel.org, hpa@zytor.com, peterz@infradead.org, mingo@kernel.org, torvalds@linux-foundation.org Reply-To: ak@linux.intel.com, linux-kernel@vger.kernel.org, torvalds@linux-foundation.org, mingo@kernel.org, hpa@zytor.com, peterz@infradead.org, stable@vger.kernel.org, tglx@linutronix.de In-Reply-To: <20161209001417.4713-1-andi@firstfloor.org> References: <20161209001417.4713-1-andi@firstfloor.org> To: linux-tip-commits@vger.kernel.org Subject: [tip:perf/core] perf/x86: Fix exclusion of BTS and LBR for Goldmont Git-Commit-ID: b0c1ef52959582144bbea9a2b37db7f4c9e399f7 X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit-ID: b0c1ef52959582144bbea9a2b37db7f4c9e399f7 Gitweb: http://git.kernel.org/tip/b0c1ef52959582144bbea9a2b37db7f4c9e399f7 Author: Andi Kleen AuthorDate: Thu, 8 Dec 2016 16:14:17 -0800 Committer: Ingo Molnar CommitDate: Sun, 11 Dec 2016 13:06:09 +0100 perf/x86: Fix exclusion of BTS and LBR for Goldmont An earlier patch allowed enabling PT and LBR at the same time on Goldmont. However it also allowed enabling BTS and LBR at the same time, which is still not supported. Fix this by bypassing the check only for PT. Signed-off-by: Andi Kleen Signed-off-by: Peter Zijlstra (Intel) Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: alexander.shishkin@intel.com Cc: kan.liang@intel.com Cc: Fixes: ccbebba4c6bf ("perf/x86/intel/pt: Bypass PT vs. LBR exclusivity if the core supports it") Link: http://lkml.kernel.org/r/20161209001417.4713-1-andi@firstfloor.org Signed-off-by: Ingo Molnar --- arch/x86/events/core.c | 8 ++++++-- arch/x86/events/perf_event.h | 2 +- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index 6e395c9..7fe88bb 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -365,7 +365,11 @@ int x86_add_exclusive(unsigned int what) { int i; - if (x86_pmu.lbr_pt_coexist) + /* + * When lbr_pt_coexist we allow PT to coexist with either LBR or BTS. + * LBR and BTS are still mutually exclusive. + */ + if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt) return 0; if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) { @@ -388,7 +392,7 @@ fail_unlock: void x86_del_exclusive(unsigned int what) { - if (x86_pmu.lbr_pt_coexist) + if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt) return; atomic_dec(&x86_pmu.lbr_exclusive[what]); diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index a77ee02..bcbb1d2 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -604,7 +604,7 @@ struct x86_pmu { u64 lbr_sel_mask; /* LBR_SELECT valid bits */ const int *lbr_sel_map; /* lbr_select mappings */ bool lbr_double_abort; /* duplicated lbr aborts */ - bool lbr_pt_coexist; /* LBR may coexist with PT */ + bool lbr_pt_coexist; /* (LBR|BTS) may coexist with PT */ /* * Intel PT/LBR/BTS are exclusive