From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753984AbbDBSqv (ORCPT ); Thu, 2 Apr 2015 14:46:51 -0400 Received: from terminus.zytor.com ([198.137.202.10]:37330 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752459AbbDBSqr (ORCPT ); Thu, 2 Apr 2015 14:46:47 -0400 Date: Thu, 2 Apr 2015 11:46:15 -0700 From: tip-bot for Andi Kleen Message-ID: Cc: tglx@linutronix.de, peterz@infradead.org, mingo@kernel.org, ak@linux.intel.com, linux-kernel@vger.kernel.org, hpa@zytor.com Reply-To: tglx@linutronix.de, peterz@infradead.org, mingo@kernel.org, ak@linux.intel.com, linux-kernel@vger.kernel.org, hpa@zytor.com In-Reply-To: <1426871484-21285-2-git-send-email-andi@firstfloor.org> References: <1426871484-21285-2-git-send-email-andi@firstfloor.org> To: linux-tip-commits@vger.kernel.org Subject: [tip:perf/core] perf/x86/intel: Avoid rewriting DEBUGCTL with the same value for LBRs Git-Commit-ID: cd1f11de69226cc7ce7e7f22bdab9010103ddaa6 X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit-ID: cd1f11de69226cc7ce7e7f22bdab9010103ddaa6 Gitweb: http://git.kernel.org/tip/cd1f11de69226cc7ce7e7f22bdab9010103ddaa6 Author: Andi Kleen AuthorDate: Fri, 20 Mar 2015 10:11:24 -0700 Committer: Ingo Molnar CommitDate: Thu, 2 Apr 2015 17:33:20 +0200 perf/x86/intel: Avoid rewriting DEBUGCTL with the same value for LBRs perf with LBRs on has a tendency to rewrite the DEBUGCTL MSR with the same value. Add a little optimization to skip the unnecessary write. Signed-off-by: Andi Kleen Signed-off-by: Peter Zijlstra (Intel) Cc: eranian@google.com Link: http://lkml.kernel.org/r/1426871484-21285-2-git-send-email-andi@firstfloor.org Signed-off-by: Ingo Molnar --- arch/x86/kernel/cpu/perf_event_intel_lbr.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/arch/x86/kernel/cpu/perf_event_intel_lbr.c index 3d53725..94e5b50 100644 --- a/arch/x86/kernel/cpu/perf_event_intel_lbr.c +++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c @@ -135,7 +135,7 @@ static void intel_pmu_lbr_filter(struct cpu_hw_events *cpuc); static void __intel_pmu_lbr_enable(bool pmi) { struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); - u64 debugctl, lbr_select = 0; + u64 debugctl, lbr_select = 0, orig_debugctl; /* * No need to reprogram LBR_SELECT in a PMI, as it @@ -147,6 +147,7 @@ static void __intel_pmu_lbr_enable(bool pmi) } rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); + orig_debugctl = debugctl; debugctl |= DEBUGCTLMSR_LBR; /* * LBR callstack does not work well with FREEZE_LBRS_ON_PMI. @@ -155,7 +156,8 @@ static void __intel_pmu_lbr_enable(bool pmi) */ if (!(lbr_select & LBR_CALL_STACK)) debugctl |= DEBUGCTLMSR_FREEZE_LBRS_ON_PMI; - wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); + if (orig_debugctl != debugctl) + wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); } static void __intel_pmu_lbr_disable(void)