From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752581AbbJTJg7 (ORCPT ); Tue, 20 Oct 2015 05:36:59 -0400 Received: from terminus.zytor.com ([198.137.202.10]:49890 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751140AbbJTJg4 (ORCPT ); Tue, 20 Oct 2015 05:36:56 -0400 Date: Tue, 20 Oct 2015 02:36:12 -0700 From: tip-bot for Stephane Eranian Message-ID: Cc: torvalds@linux-foundation.org, vincent.weaver@maine.edu, jolsa@redhat.com, namhyung@kernel.org, dsahern@gmail.com, linux-kernel@vger.kernel.org, eranian@google.com, mingo@kernel.org, tglx@linutronix.de, hpa@zytor.com, peterz@infradead.org, acme@redhat.com Reply-To: namhyung@kernel.org, jolsa@redhat.com, dsahern@gmail.com, eranian@google.com, linux-kernel@vger.kernel.org, torvalds@linux-foundation.org, vincent.weaver@maine.edu, acme@redhat.com, hpa@zytor.com, mingo@kernel.org, tglx@linutronix.de, peterz@infradead.org In-Reply-To: <1444720151-10275-3-git-send-email-eranian@google.com> References: <1444720151-10275-3-git-send-email-eranian@google.com> To: linux-tip-commits@vger.kernel.org Subject: [tip:perf/core] perf/x86: Add support for PERF_SAMPLE_BRANCH_CALL Git-Commit-ID: d892819faa6860d469aae71d70c336b391c25505 X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit-ID: d892819faa6860d469aae71d70c336b391c25505 Gitweb: http://git.kernel.org/tip/d892819faa6860d469aae71d70c336b391c25505 Author: Stephane Eranian AuthorDate: Tue, 13 Oct 2015 09:09:09 +0200 Committer: Ingo Molnar CommitDate: Tue, 20 Oct 2015 10:30:53 +0200 perf/x86: Add support for PERF_SAMPLE_BRANCH_CALL This patch enables the suport for the PERF_SAMPLE_BRANCH_CALL for Intel x86 processors. When the processor support LBR filtering this the selection is done in hardware. Otherwise, the filter is applied by software. Note that we chose to include zero length calls because they also represent calls. Signed-off-by: Stephane Eranian Signed-off-by: Peter Zijlstra (Intel) Cc: Arnaldo Carvalho de Melo Cc: David Ahern Cc: Jiri Olsa Cc: Linus Torvalds Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: Vince Weaver Cc: khandual@linux.vnet.ibm.com Link: http://lkml.kernel.org/r/1444720151-10275-3-git-send-email-eranian@google.com Signed-off-by: Ingo Molnar --- arch/x86/kernel/cpu/perf_event_intel_lbr.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/arch/x86/kernel/cpu/perf_event_intel_lbr.c index ad0b8b0..bfd0b71 100644 --- a/arch/x86/kernel/cpu/perf_event_intel_lbr.c +++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c @@ -555,6 +555,8 @@ static int intel_pmu_setup_sw_lbr_filter(struct perf_event *event) if (br_type & PERF_SAMPLE_BRANCH_IND_JUMP) mask |= X86_BR_IND_JMP; + if (br_type & PERF_SAMPLE_BRANCH_CALL) + mask |= X86_BR_CALL | X86_BR_ZERO_CALL; /* * stash actual user request into reg, it may * be used by fixup code for some CPU @@ -890,6 +892,7 @@ static const int snb_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX_SHIFT] = { [PERF_SAMPLE_BRANCH_IND_CALL_SHIFT] = LBR_IND_CALL, [PERF_SAMPLE_BRANCH_COND_SHIFT] = LBR_JCC, [PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT] = LBR_IND_JMP, + [PERF_SAMPLE_BRANCH_CALL_SHIFT] = LBR_REL_CALL, }; static const int hsw_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX_SHIFT] = { @@ -905,6 +908,7 @@ static const int hsw_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX_SHIFT] = { [PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] = LBR_REL_CALL | LBR_IND_CALL | LBR_RETURN | LBR_CALL_STACK, [PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT] = LBR_IND_JMP, + [PERF_SAMPLE_BRANCH_CALL_SHIFT] = LBR_REL_CALL, }; /* core */