From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755326AbdC3IlW (ORCPT ); Thu, 30 Mar 2017 04:41:22 -0400 Received: from terminus.zytor.com ([65.50.211.136]:42781 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754554AbdC3IlS (ORCPT ); Thu, 30 Mar 2017 04:41:18 -0400 Date: Thu, 30 Mar 2017 01:35:20 -0700 From: tip-bot for Suravee Suthikulpanit Message-ID: Cc: bp@suse.de, jolsa@redhat.com, tglx@linutronix.de, torvalds@linux-foundation.org, vincent.weaver@maine.edu, alexander.shishkin@linux.intel.com, mingo@kernel.org, eranian@google.com, joro@8bytes.org, peterz@infradead.org, linux-kernel@vger.kernel.org, acme@redhat.com, hpa@zytor.com, suravee.suthikulpanit@amd.com, Suravee.Suthikulpanit@amd.com Reply-To: vincent.weaver@maine.edu, torvalds@linux-foundation.org, tglx@linutronix.de, bp@suse.de, jolsa@redhat.com, alexander.shishkin@linux.intel.com, peterz@infradead.org, joro@8bytes.org, eranian@google.com, mingo@kernel.org, Suravee.Suthikulpanit@amd.com, suravee.suthikulpanit@amd.com, hpa@zytor.com, acme@redhat.com, linux-kernel@vger.kernel.org In-Reply-To: <1487926102-13073-4-git-send-email-Suravee.Suthikulpanit@amd.com> References: <1487926102-13073-4-git-send-email-Suravee.Suthikulpanit@amd.com> To: linux-tip-commits@vger.kernel.org Subject: [tip:perf/core] x86/events/amd/iommu: Clean up perf_iommu_read() Git-Commit-ID: dc6ca5e47d44c11a111807208595ff6a8fcd2a83 X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit-ID: dc6ca5e47d44c11a111807208595ff6a8fcd2a83 Gitweb: http://git.kernel.org/tip/dc6ca5e47d44c11a111807208595ff6a8fcd2a83 Author: Suravee Suthikulpanit AuthorDate: Fri, 24 Feb 2017 02:48:15 -0600 Committer: Ingo Molnar CommitDate: Thu, 30 Mar 2017 09:53:52 +0200 x86/events/amd/iommu: Clean up perf_iommu_read() Fix coding style and use GENMASK_ULL(). Signed-off-by: Suravee Suthikulpanit Signed-off-by: Borislav Petkov Signed-off-by: Peter Zijlstra (Intel) Cc: Alexander Shishkin Cc: Arnaldo Carvalho de Melo Cc: Jiri Olsa Cc: Jörg Rödel Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Stephane Eranian Cc: Thomas Gleixner Cc: Vince Weaver Cc: iommu@lists.linux-foundation.org Link: http://lkml.kernel.org/r/1487926102-13073-4-git-send-email-Suravee.Suthikulpanit@amd.com Signed-off-by: Ingo Molnar --- arch/x86/events/amd/iommu.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/arch/x86/events/amd/iommu.c b/arch/x86/events/amd/iommu.c index e112f49..d4375da 100644 --- a/arch/x86/events/amd/iommu.c +++ b/arch/x86/events/amd/iommu.c @@ -320,9 +320,7 @@ static void perf_iommu_start(struct perf_event *event, int flags) static void perf_iommu_read(struct perf_event *event) { - u64 count = 0ULL; - u64 prev_raw_count = 0ULL; - u64 delta = 0ULL; + u64 count, prev, delta; struct hw_perf_event *hwc = &event->hw; amd_iommu_pc_get_set_reg_val(_GET_DEVID(event), @@ -330,18 +328,16 @@ static void perf_iommu_read(struct perf_event *event) IOMMU_PC_COUNTER_REG, &count, false); /* IOMMU pc counter register is only 48 bits */ - count &= 0xFFFFFFFFFFFFULL; + count &= GENMASK_ULL(47, 0); - prev_raw_count = local64_read(&hwc->prev_count); - if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, - count) != prev_raw_count) + prev = local64_read(&hwc->prev_count); + if (local64_cmpxchg(&hwc->prev_count, prev, count) != prev) return; - /* Handling 48-bit counter overflowing */ - delta = (count << COUNTER_SHIFT) - (prev_raw_count << COUNTER_SHIFT); + /* Handle 48-bit counter overflow */ + delta = (count << COUNTER_SHIFT) - (prev << COUNTER_SHIFT); delta >>= COUNTER_SHIFT; local64_add(delta, &event->count); - } static void perf_iommu_stop(struct perf_event *event, int flags)