From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755273AbbIMLJ6 (ORCPT ); Sun, 13 Sep 2015 07:09:58 -0400 Received: from terminus.zytor.com ([198.137.202.10]:43815 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751835AbbIMLJ5 (ORCPT ); Sun, 13 Sep 2015 07:09:57 -0400 Date: Sun, 13 Sep 2015 04:09:09 -0700 From: tip-bot for Kan Liang Message-ID: Cc: mingo@kernel.org, vincent.weaver@maine.edu, eranian@google.com, mail@milianw.de, jolsa@redhat.com, hpa@zytor.com, peterz@infradead.org, linux-kernel@vger.kernel.org, tglx@linutronix.de, acme@redhat.com, kan.liang@intel.com, torvalds@linux-foundation.org Reply-To: mail@milianw.de, eranian@google.com, vincent.weaver@maine.edu, mingo@kernel.org, peterz@infradead.org, jolsa@redhat.com, hpa@zytor.com, linux-kernel@vger.kernel.org, kan.liang@intel.com, torvalds@linux-foundation.org, acme@redhat.com, tglx@linutronix.de In-Reply-To: <1439815051-8616-1-git-send-email-kan.liang@intel.com> References: <1439815051-8616-1-git-send-email-kan.liang@intel.com> To: linux-tip-commits@vger.kernel.org Subject: [tip:perf/core] perf/x86/intel: Fix LBR callstack issue caused by FREEZE_LBRS_ON_PMI Git-Commit-ID: deb27519bf1f4b21a761c0675dbdf1196df7d72a X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit-ID: deb27519bf1f4b21a761c0675dbdf1196df7d72a Gitweb: http://git.kernel.org/tip/deb27519bf1f4b21a761c0675dbdf1196df7d72a Author: Kan Liang AuthorDate: Mon, 17 Aug 2015 08:37:31 -0400 Committer: Ingo Molnar CommitDate: Sun, 13 Sep 2015 11:27:22 +0200 perf/x86/intel: Fix LBR callstack issue caused by FREEZE_LBRS_ON_PMI This patch fixes an issue which introduced by commit 1a78d93750bb5f61abdc59a91fc3bd06a214542a ("perf/x86/intel: Streamline LBR MSR handling in PMI"). The old patch not only avoids writing LBR_SELECT MSR in PMI, but also avoids updating lbr_select variable. So in PMI, FREEZE_LBRS_ON_PMI bit is always mistakenly set for IA32_DEBUGCTLMSR MSR, which causes superfluous increase/decrease of LBR_TOS when collecting LBR callstack. Reported-by: Milian Wolff Signed-off-by: Kan Liang Signed-off-by: Peter Zijlstra (Intel) Cc: Arnaldo Carvalho de Melo Cc: Jiri Olsa Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Stephane Eranian Cc: Thomas Gleixner Cc: Vince Weaver Link: http://lkml.kernel.org/r/1439815051-8616-1-git-send-email-kan.liang@intel.com Signed-off-by: Ingo Molnar --- arch/x86/kernel/cpu/perf_event_intel_lbr.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/arch/x86/kernel/cpu/perf_event_intel_lbr.c index b2c9475..a1d07c7 100644 --- a/arch/x86/kernel/cpu/perf_event_intel_lbr.c +++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c @@ -151,10 +151,9 @@ static void __intel_pmu_lbr_enable(bool pmi) * No need to reprogram LBR_SELECT in a PMI, as it * did not change. */ - if (cpuc->lbr_sel && !pmi) { - lbr_select = cpuc->lbr_sel->config; + lbr_select = cpuc->lbr_sel->config; + if (cpuc->lbr_sel && !pmi) wrmsrl(MSR_LBR_SELECT, lbr_select); - } rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); orig_debugctl = debugctl;