From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752014AbdCPLXE (ORCPT ); Thu, 16 Mar 2017 07:23:04 -0400 Received: from terminus.zytor.com ([65.50.211.136]:44548 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751342AbdCPLXC (ORCPT ); Thu, 16 Mar 2017 07:23:02 -0400 Date: Thu, 16 Mar 2017 04:22:25 -0700 From: tip-bot for Kan Liang Message-ID: Cc: alexander.shishkin@linux.intel.com, tglx@linutronix.de, eranian@google.com, linux-kernel@vger.kernel.org, peterz@infradead.org, torvalds@linux-foundation.org, vincent.weaver@maine.edu, kan.liang@intel.com, mingo@kernel.org, acme@redhat.com, jolsa@redhat.com, hpa@zytor.com Reply-To: mingo@kernel.org, kan.liang@intel.com, acme@redhat.com, jolsa@redhat.com, hpa@zytor.com, alexander.shishkin@linux.intel.com, tglx@linutronix.de, eranian@google.com, torvalds@linux-foundation.org, linux-kernel@vger.kernel.org, peterz@infradead.org, vincent.weaver@maine.edu In-Reply-To: <1486711438-80058-1-git-send-email-kan.liang@intel.com> References: <1486711438-80058-1-git-send-email-kan.liang@intel.com> To: linux-tip-commits@vger.kernel.org Subject: [tip:perf/core] perf/x86: Add Top Down events to Intel Goldmont Git-Commit-ID: ed827adb009490673c9c63e0b716e0fa36afbcc1 X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit-ID: ed827adb009490673c9c63e0b716e0fa36afbcc1 Gitweb: http://git.kernel.org/tip/ed827adb009490673c9c63e0b716e0fa36afbcc1 Author: Kan Liang AuthorDate: Fri, 10 Feb 2017 02:23:58 -0500 Committer: Ingo Molnar CommitDate: Thu, 16 Mar 2017 09:51:10 +0100 perf/x86: Add Top Down events to Intel Goldmont Goldmont supports full Top Down level 1 metrics (FrontendBound, Retiring, Backend Bound and Bad Speculation). It has 3 wide pipeline. Signed-off-by: Kan Liang Signed-off-by: Peter Zijlstra (Intel) Cc: Alexander Shishkin Cc: Arnaldo Carvalho de Melo Cc: Jiri Olsa Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Stephane Eranian Cc: Thomas Gleixner Cc: Vince Weaver Link: http://lkml.kernel.org/r/1486711438-80058-1-git-send-email-kan.liang@intel.com Signed-off-by: Ingo Molnar --- arch/x86/events/intel/core.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index eb1484c..4244bed 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -1553,6 +1553,27 @@ static __initconst const u64 slm_hw_cache_event_ids }, }; +EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c"); +EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3"); +/* UOPS_NOT_DELIVERED.ANY */ +EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c"); +/* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */ +EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02"); +/* UOPS_RETIRED.ANY */ +EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2"); +/* UOPS_ISSUED.ANY */ +EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e"); + +static struct attribute *glm_events_attrs[] = { + EVENT_PTR(td_total_slots_glm), + EVENT_PTR(td_total_slots_scale_glm), + EVENT_PTR(td_fetch_bubbles_glm), + EVENT_PTR(td_recovery_bubbles_glm), + EVENT_PTR(td_slots_issued_glm), + EVENT_PTR(td_slots_retired_glm), + NULL +}; + static struct extra_reg intel_glm_extra_regs[] __read_mostly = { /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0), @@ -3750,6 +3771,7 @@ __init int intel_pmu_init(void) x86_pmu.pebs_prec_dist = true; x86_pmu.lbr_pt_coexist = true; x86_pmu.flags |= PMU_FL_HAS_RSP_1; + x86_pmu.cpu_events = glm_events_attrs; pr_cont("Goldmont events, "); break;