From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752888AbbE0KD2 (ORCPT ); Wed, 27 May 2015 06:03:28 -0400 Received: from terminus.zytor.com ([198.137.202.10]:33420 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752466AbbE0KDZ (ORCPT ); Wed, 27 May 2015 06:03:25 -0400 Date: Wed, 27 May 2015 03:02:55 -0700 From: tip-bot for Thomas Gleixner Message-ID: Cc: peterz@infradead.org, will.auld@intel.com, kanaka.d.juvva@intel.com, vikas.shivappa@linux.intel.com, mingo@kernel.org, tglx@linutronix.de, torvalds@linux-foundation.org, linux-kernel@vger.kernel.org, matt.fleming@intel.com, hpa@zytor.com Reply-To: torvalds@linux-foundation.org, linux-kernel@vger.kernel.org, matt.fleming@intel.com, hpa@zytor.com, mingo@kernel.org, tglx@linutronix.de, peterz@infradead.org, kanaka.d.juvva@intel.com, will.auld@intel.com, vikas.shivappa@linux.intel.com In-Reply-To: <20150518235149.823214798@linutronix.de> References: <20150518235149.823214798@linutronix.de> To: linux-tip-commits@vger.kernel.org Subject: [tip:perf/core] perf/x86/intel/cqm: Document PQR MSR abuse Git-Commit-ID: f4d9757ca6f5a2db6919a5b1ab86b8afa16773d0 X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit-ID: f4d9757ca6f5a2db6919a5b1ab86b8afa16773d0 Gitweb: http://git.kernel.org/tip/f4d9757ca6f5a2db6919a5b1ab86b8afa16773d0 Author: Thomas Gleixner AuthorDate: Tue, 19 May 2015 00:00:50 +0000 Committer: Ingo Molnar CommitDate: Wed, 27 May 2015 09:17:38 +0200 perf/x86/intel/cqm: Document PQR MSR abuse The CQM code acts like it owns the PQR MSR completely. That's not true because only the lower 10 bits are used for CQM. The upper 32 bits are used for the 'CLass Of Service ID' (CLOSID). Document the abuse. Will be fixed in a later patch. Signed-off-by: Thomas Gleixner Signed-off-by: Peter Zijlstra (Intel) Acked-by: Matt Fleming Cc: Kanaka Juvva Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Vikas Shivappa Cc: Will Auld Link: http://lkml.kernel.org/r/20150518235149.823214798@linutronix.de Signed-off-by: Ingo Molnar --- arch/x86/kernel/cpu/perf_event_intel_cqm.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/perf_event_intel_cqm.c b/arch/x86/kernel/cpu/perf_event_intel_cqm.c index e4d1b8b..572582e 100644 --- a/arch/x86/kernel/cpu/perf_event_intel_cqm.c +++ b/arch/x86/kernel/cpu/perf_event_intel_cqm.c @@ -978,7 +978,12 @@ static void intel_cqm_event_start(struct perf_event *event, int mode) WARN_ON_ONCE(state->rmid); state->rmid = rmid; - wrmsrl(MSR_IA32_PQR_ASSOC, state->rmid); + /* + * This is actually wrong, as the upper 32 bit MSR contain the + * closid which is used for configuring the Cache Allocation + * Technology component. + */ + wrmsr(MSR_IA32_PQR_ASSOC, rmid, 0); raw_spin_unlock_irqrestore(&state->lock, flags); } @@ -998,7 +1003,13 @@ static void intel_cqm_event_stop(struct perf_event *event, int mode) if (!--state->cnt) { state->rmid = 0; - wrmsrl(MSR_IA32_PQR_ASSOC, 0); + /* + * This is actually wrong, as the upper 32 bit of the + * MSR contain the closid which is used for + * configuring the Cache Allocation Technology + * component. + */ + wrmsr(MSR_IA32_PQR_ASSOC, 0, 0); } else { WARN_ON_ONCE(!state->rmid); }