From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Google-Smtp-Source: AH8x225QpqnEozsv4Vn3PLvPLgwzwRKOsxQlfQppjvRzmph2tE/EheMvmD612e+zIM7X5UZCgPPQ ARC-Seal: i=1; a=rsa-sha256; t=1516978940; cv=none; d=google.com; s=arc-20160816; b=wi21LBkpeE1yAtdDUPYSQ7OfeHIhZH4v2nJM5Oj+oXzsKGOGfu7/I+lzMxJrsk2CSx MKdsmHLscujf78qUwWD3x6bAsLOgtbBt9TQTYUea2VGlJRAI5l5wtKYfUAn8BvdiACal 5LLQi94EMAN8+TzCLvAhOXVzgbMBOlUGp2hWC4jonFbVjN6GqxhqBSvDxh7qnDsw546N R1oSMUwnlPFIG9OPO/3giaAcj3/jbEEFEyLJnG28GOu5BbWCaPI6rAoJtHBnU63hCpV0 s1FZeweYAlC3czwwH7Aov9ZjBk4Z10J2Z6TlQ8DSwN4EtbrJ63NodHp99v4G+GCO+mif 54mg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=precedence:content-disposition:content-transfer-encoding :mime-version:robot-unsubscribe:robot-id:git-commit-id:subject:to :references:in-reply-to:reply-to:cc:message-id:from:sender:date :arc-authentication-results; bh=Wl8w5VP+Wn6MJeuFMd0Zhpgr/E4FxCmE2QSsjNax9Gc=; b=CKvAx7LhWLKCm72xvZcEX2eg5DTQ3mk+Qw5PDZjw2ipaO3tcPi3ISZlnJTqQp93BMC 9qx/IaR2hoXA6qsc+8YiPG4wKT0SePvNCOzXunJuT8pcbVehlDvYQSWqkP1PO/B7YNWd ZVIa6W2dn4Y3DyaVflt/ClnfK/V/WsVPbUe/giKaYhl9GfMhwc/Y9I2KHftp6er39XF0 WUmEjeZFaqTj20skB0b7mRXim9jDzPd/HZ0ULRv6FQ/GzkgII1zMEyCF/DiGLPUxYRJe QHCu46d9QKovaYgogRuPB8H5RU4Itw6LwH7WGRP6WX0aj9NNENsJGWntD9W/7YauDNDk 4/Nw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of tipbot@zytor.com designates 65.50.211.136 as permitted sender) smtp.mailfrom=tipbot@zytor.com Authentication-Results: mx.google.com; spf=pass (google.com: domain of tipbot@zytor.com designates 65.50.211.136 as permitted sender) smtp.mailfrom=tipbot@zytor.com Date: Fri, 26 Jan 2018 07:00:04 -0800 Sender: tip tree robot From: tip-bot for David Woodhouse Message-ID: Cc: linux-kernel@vger.kernel.org, gregkh@linuxfoundation.org, mingo@kernel.org, tglx@linutronix.de, hpa@zytor.com, bp@suse.de, dwmw@amazon.co.uk Reply-To: tglx@linutronix.de, hpa@zytor.com, mingo@kernel.org, linux-kernel@vger.kernel.org, gregkh@linuxfoundation.org, dwmw@amazon.co.uk, bp@suse.de In-Reply-To: <1516896855-7642-3-git-send-email-dwmw@amazon.co.uk> References: <1516896855-7642-3-git-send-email-dwmw@amazon.co.uk> To: linux-tip-commits@vger.kernel.org Subject: [tip:x86/pti] x86/cpufeatures: Add Intel feature bits for Speculation Control Git-Commit-ID: fc67dd70adb711a45d2ef34e12d1a8be75edde61 X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1590555812493666698?= X-GMAIL-MSGID: =?utf-8?q?1590667709788117663?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: Commit-ID: fc67dd70adb711a45d2ef34e12d1a8be75edde61 Gitweb: https://git.kernel.org/tip/fc67dd70adb711a45d2ef34e12d1a8be75edde61 Author: David Woodhouse AuthorDate: Thu, 25 Jan 2018 16:14:10 +0000 Committer: Thomas Gleixner CommitDate: Fri, 26 Jan 2018 15:53:16 +0100 x86/cpufeatures: Add Intel feature bits for Speculation Control Add three feature bits exposed by new microcode on Intel CPUs for speculation control. Signed-off-by: David Woodhouse Signed-off-by: Thomas Gleixner Reviewed-by: Greg Kroah-Hartman Reviewed-by: Borislav Petkov Cc: gnomes@lxorguk.ukuu.org.uk Cc: ak@linux.intel.com Cc: ashok.raj@intel.com Cc: dave.hansen@intel.com Cc: karahmed@amazon.de Cc: arjan@linux.intel.com Cc: torvalds@linux-foundation.org Cc: peterz@infradead.org Cc: bp@alien8.de Cc: pbonzini@redhat.com Cc: tim.c.chen@linux.intel.com Cc: gregkh@linux-foundation.org Link: https://lkml.kernel.org/r/1516896855-7642-3-git-send-email-dwmw@amazon.co.uk --- arch/x86/include/asm/cpufeatures.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 7b25cf3..0a51070 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -320,6 +320,9 @@ /* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */ #define X86_FEATURE_AVX512_4VNNIW (18*32+ 2) /* AVX-512 Neural Network Instructions */ #define X86_FEATURE_AVX512_4FMAPS (18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */ +#define X86_FEATURE_SPEC_CTRL (18*32+26) /* Speculation Control (IBRS + IBPB) */ +#define X86_FEATURE_STIBP (18*32+27) /* Single Thread Indirect Branch Predictors */ +#define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */ /* * BUG word(s)