Re: [PATCH + an old question] firewire: ohci: use memory barriers to order descriptor updates

[Stefan Richter <stefanr@s5r6.in-berlin.de>]

On 27 Jul, Stefan Richter wrote:
> 2. a write memory barrier between branch_address update and wake-up of
>    the DMA unit by MMIO register write.
> 
> This patch adds only barrier 1.
> 
> Barrier 2 is implicit in writel() on most machines --- or at least I
> think it is.  See this from arch/alpha/include/asm/io.h:

Typo, arch/x86/include/asm/io.h was meant.

>     #define build_mmio_write(name, size, type, reg, barrier) \
>     static inline void name(type val, volatile void __iomem *addr) \
>     { asm volatile("mov" size " %0,%1": :reg (val), \
>     "m" (*(volatile type __force *)addr) barrier); }
> 
>     build_mmio_write(writel, "l", unsigned int, "r", :"memory")
> 
> Does this order the mmio write relative to previous memory writes?
-- 
Stefan Richter
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