Re: [PATCH] sata_sil24: Use memory barriers before issuing commands

[Catalin Marinas <catalin.marinas@arm.com>]

Hi Grant,

Grant Grundler <grundler@google.com> wrote:
> On Thu, Jun 10, 2010 at 7:57 AM, Catalin Marinas
> <catalin.marinas@arm.com> wrote:
>> The data in the cmd_block buffers may reach the main memory after the
>> writel() to the device ports.
>
> "ia-64 Linux Kernel" (mosberger and eranian) uses exactly this sequence
> as an example for wmb() on page 303.
>
> I'm curious about the system that exposed this problem. I believe wmb() fixes
>  an issue not exposed on most machines. Can any general comments be
> made about cache coherency, memory ordering (weak?), instruction ordering
>  (super scalar?), etc. ?
>
> The explanation above is a bit short (most people won't understand it).

I already posted a second version of this patch, though it triggered a
longer discussion on whether we should do this (cross-post between LKML,
linux-ide and linux-arch):

http://thread.gmane.org/gmane.linux.ide/46414

I know IA-64 and a several other architectures have weak memory ordering
but some of them just add barriers in the I/O accessors (with some
performance penalty).

Since the (new) patch is already in mainline, please comment on the other
thread for memory ordering etc.

Thanks.

-- 
Catalin