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dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from SJ2PR12MB9161.namprd12.prod.outlook.com (2603:10b6:a03:566::20) by DS2PR12MB927960.namprd12.prod.outlook.com (2603:10b6:8:403::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.546.22; Wed, 28 Oct 2026 02:04:24 +0000 Received: from SJ2PR12MB9161.namprd12.prod.outlook.com ([fe80::d9d1:8c49:a703:b017]) by SJ2PR12MB9161.namprd12.prod.outlook.com ([fe80::d9d1:8c49:a703:b017%5]) with mapi id 15.21.0546.021; Wed, 28 Oct 2026 02:04:24 +0000 From: Mikko Perttunen To: Thierry Reding , David Airlie , Simona Vetter , Jonathan Hunter , linux-tegra@vger.kernel.org Cc: Thierry Reding , dri-devel@lists.freedesktop.org, Svyatoslav Ryhel , linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Patrick Fischer , admin@tsv-stahl-riesa.de Subject: Re: [PATCH] gpu: host1x: mipi: Disable clock again after powering down the pads Date: Wed, 28 Oct 2026 11:04:20 +0900 Message-ID: In-Reply-To: <20261025-upstream-host1x-mipi-clk-v1-1-6bc6e755b4cb@tsv-stahl-riesa.de> References: <20261025-upstream-host1x-mipi-clk-v1-1-6bc6e755b4cb@tsv-stahl-riesa.de> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; 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Every disable/enable cycle > of a DSI or CSI user therefore leaks one enable count, and the clock > stays on for good after the first power down. >=20 > Add the missing clk_disable(), matching tegra114_mipi_power_up(). >=20 > The leak gets more costly with "clk: tegra: Fix Tegra114 MIPI > calibration clock parent", which makes PLL_P_OUT3 the parent of > mipi-cal: without this fix PLL_P_OUT3 would then stay on as well. >=20 > On a Tegra Note 7 (P1640) the enable count of mipi-cal in clk_summary > grew by one with each DPMS off/on cycle of the DSI panel. With this > patch it returns to 0 after each cycle. >=20 > Fixes: 15372d4be7f0 ("gpu: host1x: mipi: Power down regulators when unuse= d") > Signed-off-by: Patrick Fischer > --- > Mikko's "clk: tegra: Fix Tegra114 MIPI calibration clock parent" [1] > fixes the MIPI calibration timeouts on Tegra114. While testing the same > change on a Tegra Note 7 (P1640) I noticed that > tegra114_mipi_power_down() leaks the clock enable it takes. With [1] > applied that leak keeps PLL_P_OUT3 on after the first DPMS off, so the > two belong together, although this patch applies and makes sense on > its own. >=20 > [1] https://lore.kernel.org/all/20260930-b4-dalmore-fixes-mipical-clk-v1-= 1-0518be6c7979@nvidia.com/ >=20 > Tool use (see Documentation/process/generated-content.rst): this patch, > its changelog and this note were prepared with an LLM coding assistant > (Claude Code). It traced the clock enable counts from my clk_summary > dumps and wrote the code change and the texts from my measurements and > instructions. I reviewed the change and ran the test on the device. > --- > drivers/gpu/host1x/tegra114-mipi.c | 2 ++ > 1 file changed, 2 insertions(+) >=20 > diff --git a/drivers/gpu/host1x/tegra114-mipi.c b/drivers/gpu/host1x/tegr= a114-mipi.c > index c084a09784d1..83a43a5e33af 100644 > --- a/drivers/gpu/host1x/tegra114-mipi.c > +++ b/drivers/gpu/host1x/tegra114-mipi.c > @@ -197,6 +197,8 @@ static int tegra114_mipi_power_down(struct tegra_mipi= *mipi) > value |=3D MIPI_CAL_BIAS_PAD_PDVCLAMP; > tegra_mipi_writel(mipi, value, MIPI_CAL_BIAS_PAD_CFG0); > =20 > + clk_disable(mipi->clk); > + > return 0; > } > =20 >=20 > --- > base-commit: 734bef548a96e8774d6eef5dfa2026c6edc4e80b > change-id: 20261025-upstream-host1x-mipi-clk-867edad177b0 >=20 > Best regards, > -- =20 > Patrick Fischer Thanks! Reviewed-by: Mikko Perttunen