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For example, yuv420 is supported but yvu420 is > > not. This can be efficiently worked around by just passing the hardware > > said chroma planes backwards. Add a flag to the plane state struct and > > handling to both tegradc and nvdisplay paths. > >=20 > > Signed-off-by: Aaron Kling > > --- > > drivers/gpu/drm/tegra/dc.c | 17 ++++++++++++----- > > drivers/gpu/drm/tegra/hub.c | 14 +++++++++----- > > drivers/gpu/drm/tegra/plane.c | 4 +++- > > drivers/gpu/drm/tegra/plane.h | 3 ++- > > 4 files changed, 26 insertions(+), 12 deletions(-) > >=20 > > diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c > > index b0bfa946e6979..76d3841a17b8b 100644 > > --- a/drivers/gpu/drm/tegra/dc.c > > +++ b/drivers/gpu/drm/tegra/dc.c > > @@ -444,7 +444,8 @@ tegra_plane_use_vertical_filtering(struct tegra_pla= ne *plane, > > } > > =20 > > static void tegra_dc_setup_window(struct tegra_plane *plane, > > - const struct tegra_dc_window *window) > > + const struct tegra_dc_window *window, > > + struct tegra_plane_state *tegra_plane_state) > > { > > unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp; > > struct tegra_dc *dc =3D plane->dc; > > @@ -510,10 +511,13 @@ static void tegra_dc_setup_window(struct tegra_pl= ane *plane, > > tegra_plane_writel(plane, window->base[0], DC_WINBUF_START_ADDR); > > =20 > > if (yuv && planes > 1) { > > - tegra_plane_writel(plane, window->base[1], DC_WINBUF_START_ADDR_U); > > + uint8_t u =3D tegra_plane_state->swap_uv ? 2 : 1; > > + uint8_t v =3D tegra_plane_state->swap_uv ? 1 : 2; > > + > > + tegra_plane_writel(plane, window->base[u], DC_WINBUF_START_ADDR_U); > > =20 > > if (planes > 2) > > - tegra_plane_writel(plane, window->base[2], DC_WINBUF_START_ADDR_V); > > + tegra_plane_writel(plane, window->base[v], DC_WINBUF_START_ADDR_V); > > =20 > > value =3D window->stride[1] << 16 | window->stride[0]; > > tegra_plane_writel(plane, value, DC_WIN_LINE_STRIDE); > > @@ -740,7 +744,8 @@ static int tegra_plane_atomic_check(struct drm_plan= e *plane, > > =20 > > err =3D tegra_plane_format(new_plane_state->fb->format->format, > > &plane_state->format, > > - &plane_state->swap); > > + &plane_state->swap, > > + &plane_state->swap_uv); > > if (err < 0) > > return err; > > =20 > > @@ -871,8 +876,10 @@ static void tegra_plane_atomic_update(struct drm_p= lane *plane, > > if (i < 2) > > window.stride[i] =3D fb->pitches[i]; > > } > > + if (tegra_plane_state->swap_uv) > > + window.stride[1] =3D fb->pitches[2]; >=20 > Based on the comment above, U and V have the same stride, so this > isn't required. >=20 > > =20 > > - tegra_dc_setup_window(p, &window); > > + tegra_dc_setup_window(p, &window, tegra_plane_state); >=20 > Instead of passing the plane state, I'd just add a >=20 > swap(window.base[1], window.base[2]); >=20 > here. >=20 > Otherwise looks good to me! I also tested on AGX Xavier. >=20 > Mikko (Well, sashiko has some findings, please check them as well) >=20 > > } > > =20 > > static const struct drm_plane_helper_funcs tegra_plane_helper_funcs = =3D { > > diff --git a/drivers/gpu/drm/tegra/hub.c b/drivers/gpu/drm/tegra/hub.c > > index 448f49f3a7d7e..6427155ac4fdf 100644 > > --- a/drivers/gpu/drm/tegra/hub.c > > +++ b/drivers/gpu/drm/tegra/hub.c > > @@ -440,7 +440,8 @@ static int tegra_shared_plane_atomic_check(struct d= rm_plane *plane, > > =20 > > err =3D tegra_plane_format(new_plane_state->fb->format->format, > > &plane_state->format, > > - &plane_state->swap); > > + &plane_state->swap, > > + &plane_state->swap_uv); > > if (err < 0) > > return err; > > =20 > > @@ -664,24 +665,27 @@ static void tegra_shared_plane_atomic_update(stru= ct drm_plane *plane, > > tegra_plane_writel(p, value, DC_WIN_PLANAR_STORAGE); > > =20 > > if (yuv && planes > 1) { > > - base =3D tegra_plane_state->iova[1] + fb->offsets[1]; > > + uint8_t u =3D tegra_plane_state->swap_uv ? 2 : 1; > > + uint8_t v =3D tegra_plane_state->swap_uv ? 1 : 2; > > + > > + base =3D tegra_plane_state->iova[u] + fb->offsets[u]; > > base |=3D addr_flag; > > =20 > > tegra_plane_writel(p, upper_32_bits(base), DC_WINBUF_START_ADDR_HI_U= ); > > tegra_plane_writel(p, lower_32_bits(base), DC_WINBUF_START_ADDR_U); > > =20 > > if (planes > 2) { > > - base =3D tegra_plane_state->iova[2] + fb->offsets[2]; > > + base =3D tegra_plane_state->iova[v] + fb->offsets[v]; > > base |=3D addr_flag; > > =20 > > tegra_plane_writel(p, upper_32_bits(base), DC_WINBUF_START_ADDR_HI_= V); > > tegra_plane_writel(p, lower_32_bits(base), DC_WINBUF_START_ADDR_V); > > } > > =20 > > - value =3D PITCH_U(fb->pitches[1]); > > + value =3D PITCH_U(fb->pitches[u]); > > =20 > > if (planes > 2) > > - value |=3D PITCH_V(fb->pitches[2]); > > + value |=3D PITCH_V(fb->pitches[v]); > > =20 > > tegra_plane_writel(p, value, DC_WIN_PLANAR_STORAGE_UV); > > } else { > > diff --git a/drivers/gpu/drm/tegra/plane.c b/drivers/gpu/drm/tegra/plan= e.c > > index 2148b0c59815c..f4feec62ac023 100644 > > --- a/drivers/gpu/drm/tegra/plane.c > > +++ b/drivers/gpu/drm/tegra/plane.c > > @@ -319,11 +319,13 @@ int tegra_plane_state_add(struct tegra_plane *pla= ne, > > return 0; > > } > > =20 > > -int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap) > > +int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap, bool *swap_= uv) > > { > > /* assume no swapping of fetched data */ > > if (swap) > > *swap =3D BYTE_SWAP_NOSWAP; > > + if (swap_uv) > > + *swap_uv =3D false; > > =20 > > switch (fourcc) { > > case DRM_FORMAT_ARGB4444: > > diff --git a/drivers/gpu/drm/tegra/plane.h b/drivers/gpu/drm/tegra/plan= e.h > > index e33a581e6490e..dba5f1b254e98 100644 > > --- a/drivers/gpu/drm/tegra/plane.h > > +++ b/drivers/gpu/drm/tegra/plane.h > > @@ -49,6 +49,7 @@ struct tegra_plane_state { > > struct tegra_bo_tiling tiling; > > u32 format; > > u32 swap; > > + bool swap_uv; > > =20 > > bool reflect_x; > > bool reflect_y; > > @@ -88,7 +89,7 @@ void tegra_plane_cleanup_fb(struct drm_plane *plane, > > int tegra_plane_state_add(struct tegra_plane *plane, > > struct drm_plane_state *state); > > =20 > > -int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap); > > +int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap, bool *swap_= uv); > > bool tegra_plane_format_is_indexed(unsigned int format); > > bool tegra_plane_format_is_yuv(unsigned int format, unsigned int *plan= es, unsigned int *bpc); > > int tegra_plane_setup_legacy_state(struct tegra_plane *tegra, > >=20 > > --=20 > > 2.54.0 > >=20 > >=20 > >=20 >=20 >=20 >=20 >=20