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There are two main differences > from the original Tegra210: >=20 > * There is no mem thermal sensor > * Pdiv and pdiv_ate differ tsample is also changed >=20 > Based-on: https://gitlab.com/nvidia/nv-tegra/linux-5.10/-/commit/b15149a1= 5154e6b2fc827f4f169e37c9e5b389d9 > Based-on-patch-by: Srikar Srimath Tirumala > Co-developed-by: Eugene Vernik > Signed-off-by: Eugene Vernik > Signed-off-by: Aaron Kling > --- > thermal: tegra: Add Tegra210B01 Support > --- > drivers/thermal/tegra/soctherm.c | 4 + > drivers/thermal/tegra/soctherm.h | 1 + > drivers/thermal/tegra/tegra210-soctherm.c | 133 ++++++++++++++++++++++++= ++++++ > 3 files changed, 138 insertions(+) >=20 > diff --git a/drivers/thermal/tegra/soctherm.c b/drivers/thermal/tegra/soc= therm.c > index d8e988a0d43e9..95451d1bd4e62 100644 > --- a/drivers/thermal/tegra/soctherm.c > +++ b/drivers/thermal/tegra/soctherm.c > @@ -2082,6 +2082,10 @@ static const struct of_device_id tegra_soctherm_of= _match[] =3D { > .compatible =3D "nvidia,tegra210-soctherm", > .data =3D &tegra210_soctherm, > }, > + { > + .compatible =3D "nvidia,tegra210b01-soctherm", > + .data =3D &tegra210b01_soctherm, > + }, > #endif > { }, > }; > diff --git a/drivers/thermal/tegra/soctherm.h b/drivers/thermal/tegra/soc= therm.h > index aa4af9268b05d..4bc1e44e28827 100644 > --- a/drivers/thermal/tegra/soctherm.h > +++ b/drivers/thermal/tegra/soctherm.h > @@ -156,6 +156,7 @@ extern const struct tegra_soctherm_soc tegra132_socth= erm; > =20 > #ifdef CONFIG_ARCH_TEGRA_210_SOC > extern const struct tegra_soctherm_soc tegra210_soctherm; > +extern const struct tegra_soctherm_soc tegra210b01_soctherm; > #endif > =20 > #endif > diff --git a/drivers/thermal/tegra/tegra210-soctherm.c b/drivers/thermal/= tegra/tegra210-soctherm.c > index f6e1493f0202f..b4f2c7837fd69 100644 > --- a/drivers/thermal/tegra/tegra210-soctherm.c > +++ b/drivers/thermal/tegra/tegra210-soctherm.c > @@ -44,6 +44,14 @@ static const struct tegra_tsensor_configuration tegra2= 10_tsensor_config =3D { > .tsample_ate =3D 480, > }; > =20 > +static const struct tegra_tsensor_configuration tegra210b01_tsensor_conf= ig =3D { > + .tall =3D 16300, > + .tiddq_en =3D 1, > + .ten_count =3D 1, > + .tsample =3D 240, > + .tsample_ate =3D 480, > +}; > + > static const struct tegra_tsensor_group tegra210_tsensor_group_cpu =3D { > .id =3D TEGRA124_SOCTHERM_SENSOR_CPU, > .name =3D "cpu", > @@ -63,6 +71,25 @@ static const struct tegra_tsensor_group tegra210_tsens= or_group_cpu =3D { > .thermctl_lvl0_dn_thresh_mask =3D TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK= , > }; > =20 > +static const struct tegra_tsensor_group tegra210b01_tsensor_group_cpu = =3D { > + .id =3D TEGRA124_SOCTHERM_SENSOR_CPU, > + .name =3D "cpu", > + .sensor_temp_offset =3D SENSOR_TEMP1, > + .sensor_temp_mask =3D SENSOR_TEMP1_CPU_TEMP_MASK, > + .pdiv =3D 12, > + .pdiv_ate =3D 6, > + .pdiv_mask =3D SENSOR_PDIV_CPU_MASK, > + .pllx_hotspot_diff =3D 10, > + .pllx_hotspot_mask =3D SENSOR_HOTSPOT_CPU_MASK, > + .thermtrip_any_en_mask =3D TEGRA210_THERMTRIP_ANY_EN_MASK, > + .thermtrip_enable_mask =3D TEGRA210_THERMTRIP_CPU_EN_MASK, > + .thermtrip_threshold_mask =3D TEGRA210_THERMTRIP_CPU_THRESH_MASK, > + .thermctl_isr_mask =3D THERM_IRQ_CPU_MASK, > + .thermctl_lvl0_offset =3D THERMCTL_LEVEL0_GROUP_CPU, > + .thermctl_lvl0_up_thresh_mask =3D TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK= , > + .thermctl_lvl0_dn_thresh_mask =3D TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK= , > +}; > + > static const struct tegra_tsensor_group tegra210_tsensor_group_gpu =3D { > .id =3D TEGRA124_SOCTHERM_SENSOR_GPU, > .name =3D "gpu", > @@ -82,6 +109,25 @@ static const struct tegra_tsensor_group tegra210_tsen= sor_group_gpu =3D { > .thermctl_lvl0_dn_thresh_mask =3D TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK= , > }; > =20 > +static const struct tegra_tsensor_group tegra210b01_tsensor_group_gpu = =3D { > + .id =3D TEGRA124_SOCTHERM_SENSOR_GPU, > + .name =3D "gpu", > + .sensor_temp_offset =3D SENSOR_TEMP1, > + .sensor_temp_mask =3D SENSOR_TEMP1_GPU_TEMP_MASK, > + .pdiv =3D 12, > + .pdiv_ate =3D 6, > + .pdiv_mask =3D SENSOR_PDIV_GPU_MASK, > + .pllx_hotspot_diff =3D 5, > + .pllx_hotspot_mask =3D SENSOR_HOTSPOT_GPU_MASK, > + .thermtrip_any_en_mask =3D TEGRA210_THERMTRIP_ANY_EN_MASK, > + .thermtrip_enable_mask =3D TEGRA210_THERMTRIP_GPU_EN_MASK, > + .thermtrip_threshold_mask =3D TEGRA210_THERMTRIP_GPUMEM_THRESH_MASK, > + .thermctl_isr_mask =3D THERM_IRQ_GPU_MASK, > + .thermctl_lvl0_offset =3D THERMCTL_LEVEL0_GROUP_GPU, > + .thermctl_lvl0_up_thresh_mask =3D TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK= , > + .thermctl_lvl0_dn_thresh_mask =3D TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK= , > +}; > + > static const struct tegra_tsensor_group tegra210_tsensor_group_pll =3D { > .id =3D TEGRA124_SOCTHERM_SENSOR_PLLX, > .name =3D "pll", > @@ -99,6 +145,23 @@ static const struct tegra_tsensor_group tegra210_tsen= sor_group_pll =3D { > .thermctl_lvl0_dn_thresh_mask =3D TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK= , > }; > =20 > +static const struct tegra_tsensor_group tegra210b01_tsensor_group_pll = =3D { > + .id =3D TEGRA124_SOCTHERM_SENSOR_PLLX, > + .name =3D "pll", > + .sensor_temp_offset =3D SENSOR_TEMP2, > + .sensor_temp_mask =3D SENSOR_TEMP2_PLLX_TEMP_MASK, > + .pdiv =3D 12, > + .pdiv_ate =3D 6, > + .pdiv_mask =3D SENSOR_PDIV_PLLX_MASK, > + .thermtrip_any_en_mask =3D TEGRA210_THERMTRIP_ANY_EN_MASK, > + .thermtrip_enable_mask =3D TEGRA210_THERMTRIP_TSENSE_EN_MASK, > + .thermtrip_threshold_mask =3D TEGRA210_THERMTRIP_TSENSE_THRESH_MASK, > + .thermctl_isr_mask =3D THERM_IRQ_TSENSE_MASK, > + .thermctl_lvl0_offset =3D THERMCTL_LEVEL0_GROUP_TSENSE, > + .thermctl_lvl0_up_thresh_mask =3D TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK= , > + .thermctl_lvl0_dn_thresh_mask =3D TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK= , > +}; > + > static const struct tegra_tsensor_group tegra210_tsensor_group_mem =3D { > .id =3D TEGRA124_SOCTHERM_SENSOR_MEM, > .name =3D "mem", > @@ -125,6 +188,12 @@ static const struct tegra_tsensor_group *tegra210_ts= ensor_groups[] =3D { > &tegra210_tsensor_group_mem, > }; > =20 > +static const struct tegra_tsensor_group *tegra210b01_tsensor_groups[] = =3D { > + &tegra210b01_tsensor_group_cpu, > + &tegra210b01_tsensor_group_gpu, > + &tegra210b01_tsensor_group_pll, > +}; > + > static const struct tegra_tsensor tegra210_tsensors[] =3D { > { > .name =3D "cpu0", > @@ -193,6 +262,58 @@ static const struct tegra_tsensor tegra210_tsensors[= ] =3D { > }, > }; > =20 > +static const struct tegra_tsensor tegra210b01_tsensors[] =3D { > + { > + .name =3D "cpu0", > + .base =3D 0xc0, > + .config =3D &tegra210b01_tsensor_config, > + .calib_fuse_offset =3D 0x098, > + .fuse_corr_alpha =3D 1085000, > + .fuse_corr_beta =3D 3244200, > + .group =3D &tegra210b01_tsensor_group_cpu, > + }, { > + .name =3D "cpu1", > + .base =3D 0xe0, > + .config =3D &tegra210b01_tsensor_config, > + .calib_fuse_offset =3D 0x084, > + .fuse_corr_alpha =3D 1126200, > + .fuse_corr_beta =3D -67500, > + .group =3D &tegra210b01_tsensor_group_cpu, > + }, { > + .name =3D "cpu2", > + .base =3D 0x100, > + .config =3D &tegra210b01_tsensor_config, > + .calib_fuse_offset =3D 0x088, > + .fuse_corr_alpha =3D 1098400, > + .fuse_corr_beta =3D 2251100, > + .group =3D &tegra210b01_tsensor_group_cpu, > + }, { > + .name =3D "cpu3", > + .base =3D 0x120, > + .config =3D &tegra210b01_tsensor_config, > + .calib_fuse_offset =3D 0x12c, > + .fuse_corr_alpha =3D 1108000, > + .fuse_corr_beta =3D 602700, > + .group =3D &tegra210b01_tsensor_group_cpu, > + }, { > + .name =3D "gpu", > + .base =3D 0x180, > + .config =3D &tegra210b01_tsensor_config, > + .calib_fuse_offset =3D 0x154, > + .fuse_corr_alpha =3D 1074300, > + .fuse_corr_beta =3D 2734900, > + .group =3D &tegra210b01_tsensor_group_gpu, > + }, { > + .name =3D "pllx", > + .base =3D 0x1a0, > + .config =3D &tegra210b01_tsensor_config, > + .calib_fuse_offset =3D 0x160, > + .fuse_corr_alpha =3D 1039700, > + .fuse_corr_beta =3D 6829100, > + .group =3D &tegra210b01_tsensor_group_pll, > + }, > +}; > + > /* > * Mask/shift bits in FUSE_TSENSOR_COMMON and > * FUSE_TSENSOR_COMMON, which are described in > @@ -230,3 +351,15 @@ const struct tegra_soctherm_soc tegra210_soctherm = =3D { > .use_ccroc =3D false, > .thermtrips =3D tegra210_tsensor_thermtrips, > }; > + > +const struct tegra_soctherm_soc tegra210b01_soctherm =3D { > + .tsensors =3D tegra210b01_tsensors, > + .num_tsensors =3D ARRAY_SIZE(tegra210b01_tsensors), > + .ttgs =3D tegra210b01_tsensor_groups, > + .num_ttgs =3D ARRAY_SIZE(tegra210b01_tsensor_groups), One issue in soctherm.c appears with this since the ttg ID space isn't=20 compact anymore. The array thermctl_tzs[ID] is only allocated to size soc->num_ttgs,=20 which isn't enough when there are gaps. The array should really be of=20 length TEGRA124_SOCTHERM_SENSOR_NUM. Can you add a patch to change that? Thanks Mikko > + .tfuse =3D &tegra210_soctherm_fuse, > + .thresh_grain =3D TEGRA210_THRESH_GRAIN, > + .bptt =3D TEGRA210_BPTT, > + .use_ccroc =3D false, > + .thermtrips =3D tegra210_tsensor_thermtrips, > +}; >=20 > --- > base-commit: 49362394dad7df66c274c867a271394c10ca2bb8 > change-id: 20260714-t210b01-thermal-227e6cfd2574 >=20 > Best regards, > --=20 > Aaron Kling >=20 >=20 >=20