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From: Jes Sorensen <jes@sgi.com>
To: Chase Venters <chase.venters@clientec.com>
Cc: Chris Friesen <cfriesen@nortel.com>, linux-kernel@vger.kernel.org
Subject: Re: cacheline alignment and per-cpu data
Date: 12 Jun 2006 05:17:53 -0400	[thread overview]
Message-ID: <yq0mzci3f7i.fsf@jaguar.mkp.net> (raw)
In-Reply-To: <Pine.LNX.4.64.0606091054180.4969@turbotaz.ourhouse>

>>>>> "Chase" == Chase Venters <chase.venters@clientec.com> writes:

Chase> On Fri, 9 Jun 2006, Chris Friesen wrote:
>> Will this cause cacheline pingpong?  If I do this sort of thing do
>> I need to ensure that the struct is a multiple of cacheline size
>> (or specify cacheline alignement)?

Chase> Yes. If CPU 2 tries to write to struct member 1 of array
Chase> element 2, and array element 1 is in CPU 1's cache, it must be
Chase> invalidated.

Chase> GCC (and kernel macros) provide good support for enforced
Chase> cacheline alignment, but it's also possible to pad your
Chase> structures.

Best way to go is to use __cacheline_aligned rather than try to get
the padding right manually. Someone will add a field somewhere in the
middle and mess it up and nobody notices.

Cheers,
Jes

      reply	other threads:[~2006-06-12  9:17 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2006-06-09 15:40 Chris Friesen
2006-06-09 15:56 ` Chase Venters
2006-06-12  9:17   ` Jes Sorensen [this message]

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