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From: Aneesh Kumar K.V <aneesh.kumar@kernel.org>
To: Catalin Marinas <catalin.marinas@arm.com>
Cc: iommu@lists.linux.dev, linux-kernel@vger.kernel.org,
	Robin Murphy <robin.murphy@arm.com>,
	Marek Szyprowski <m.szyprowski@samsung.com>,
	Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
	Steven Price <steven.price@arm.com>,
	Suzuki K Poulose <Suzuki.Poulose@arm.com>,
	Jiri Pirko <jiri@resnulli.us>, Jason Gunthorpe <jgg@ziepe.ca>,
	Mostafa Saleh <smostafa@google.com>,
	Petr Tesarik <ptesarik@suse.com>,
	Alexey Kardashevskiy <aik@amd.com>,
	Dan Williams <dan.j.williams@intel.com>,
	Xu Yilun <yilun.xu@linux.intel.com>,
	Madhavan Srinivasan <maddy@linux.ibm.com>,
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	Borislav Petkov <bp@alien8.de>,
	Dave Hansen <dave.hansen@linux.intel.com>,
	linux-arm-kernel@lists.infradead.org, loongarch@lists.linux.dev,
	linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org,
	linux-riscv@lists.infradead.org, linux-s390@vger.kernel.org,
	x86@kernel.org
Subject: Re: [PATCH v4 2/5] dma: swiotlb: Centralize minimal pool sizing
Date: Fri, 18 Sep 2026 12:35:33 +0530	[thread overview]
Message-ID: <yq5a4ifn11ky.fsf@kernel.org> (raw)
In-Reply-To: <aqwLiHQb71hU8cEy@arm.com>

Catalin Marinas <catalin.marinas@arm.com> writes:

> On Mon, Sep 14, 2026 at 12:31:31PM +0530, Aneesh Kumar K.V (Arm) wrote:
>> NOTE: We lose the RISC-V SWIOTLB_ANY setting in this patch. It will be
>> reinstated in a follow-up patch where we make SWIOTLB_ANY redundant.
>
> [...]
>
>> diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
>> index e0e4c103d603..734712230f35 100644
>> --- a/arch/riscv/mm/init.c
>> +++ b/arch/riscv/mm/init.c
>> @@ -165,31 +165,11 @@ static void print_vm_layout(void) { }
>>  
>>  void __init arch_mm_preinit(void)
>>  {
>> -	bool swiotlb = max_pfn > PFN_DOWN(dma32_phys_limit) &&
>> -		       memblock_start_of_DRAM() < dma32_phys_limit;
>>  	unsigned int swiotlb_flags = SWIOTLB_VERBOSE;
>>  #ifdef CONFIG_FLATMEM
>>  	BUG_ON(!mem_map);
>>  #endif /* CONFIG_FLATMEM */
>>  
>> -	if (IS_ENABLED(CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC) && !swiotlb &&
>> -	    dma_cache_alignment != 1) {
>> -		/*
>> -		 * No 32-bit DMA bouncing needed (either all DRAM is within
>> -		 * the 32-bit limit, or it all starts above it), but
>> -		 * kmalloc() buffers whose sizes are not cache-line-aligned
>> -		 * still require bouncing for non-coherent DMA.  Use
>> -		 * SWIOTLB_ANY so that the buffer can be allocated from high
>> -		 * memory when DRAM starts above dma32_phys_limit.  Allocate
>> -		 * ~1 MB per 1 GB of RAM.
>> -		 */
>> -		unsigned long size =
>> -			DIV_ROUND_UP(memblock_phys_mem_size(), 1024);
>> -		swiotlb_adjust_size(min(swiotlb_size_or_default(), size));
>> -		swiotlb = true;
>> -		swiotlb_flags |= SWIOTLB_ANY;
>> -	}
>
> Does it break the bisectability for risc-v? IIUC this undoes commit
> cfca5a48b03f until patch 5. Basically if there's no low memory and no
> SWIOTLB_ANY passed, memblock_alloc_low() will fail.
>

I mentioned this in the commit message. I can add the change below and
remove it in patch 5. 

modified   arch/riscv/mm/init.c
@@ -165,11 +165,27 @@ static void print_vm_layout(void) { }
 
 void __init arch_mm_preinit(void)
 {
+	bool swiotlb = max_pfn > PFN_DOWN(dma32_phys_limit) &&
+		       memblock_start_of_DRAM() < dma32_phys_limit;
 	unsigned int swiotlb_flags = SWIOTLB_VERBOSE;
 #ifdef CONFIG_FLATMEM
 	BUG_ON(!mem_map);
 #endif /* CONFIG_FLATMEM */
 
+	if (IS_ENABLED(CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC) && !swiotlb &&
+	    dma_cache_alignment != 1) {
+		/*
+		 * No 32-bit DMA bouncing needed (either all DRAM is within
+		 * the 32-bit limit, or it all starts above it), but
+		 * kmalloc() buffers whose sizes are not cache-line-aligned
+		 * still require bouncing for non-coherent DMA.  Use
+		 * SWIOTLB_ANY so that the buffer can be allocated from high
+		 * memory when DRAM starts above dma32_phys_limit.  Allocate
+		 * ~1 MB per 1 GB of RAM.
+		 */
+		swiotlb_flags |= SWIOTLB_ANY;
+	}
+
 	if ((max_pfn > PFN_DOWN(dma32_phys_limit)) &&
 	     (memblock_start_of_DRAM() < dma32_phys_limit))
 		swiotlb_flags |= SWIOTLB_INIT_ADDRESSING_LIMIT;


>
> I think we could preserve SWIOTLB_ANY until patch 5. Or it might be
> simpler to move patches 2 and 3 at the end (I haven't tried).
>
>> diff --git a/kernel/dma/swiotlb.c b/kernel/dma/swiotlb.c
>> index aa19e81ae544..90e0bfd0715c 100644
>> --- a/kernel/dma/swiotlb.c
>> +++ b/kernel/dma/swiotlb.c
>> @@ -304,6 +304,11 @@ unsigned long swiotlb_size_or_default(void)
>>  	return default_nslabs << IO_TLB_SHIFT;
>>  }
>>  
>> +static bool __init swiotlb_default_size_changed(void)
>> +{
>> +	return default_nslabs != IO_TLB_DEFAULT_SIZE >> IO_TLB_SHIFT;
>> +}
>
> I mentioned before in passing
> (https://lore.kernel.org/all/ann6noRzoPLL9kDY@arm.com/), if one sets
> swiotlb= to the default size, it will go unnoticed. I know it's an
> existing issue but we might as well fix it now with a bool that tells us
> the swiotlb size was forced/changed.
>

I will do this as an addtional patch

modified    kernel/dma/swiotlb.c
@@ -108,6 +108,7 @@
 
 static unsigned long default_nslabs = IO_TLB_DEFAULT_SIZE >> IO_TLB_SHIFT;
 static unsigned long default_nareas;
+static bool swiotlb_size_set __initdata;
 
 /**
  * struct io_tlb_area - IO TLB memory area descriptor
@@ -270,6 +271,7 @@
 		/* avoid tail segment of size < IO_TLB_SEGSIZE */
 		default_nslabs =
 			ALIGN(simple_strtoul(str, &str, 0), IO_TLB_SEGSIZE);
+		swiotlb_size_set = true;
 	}
 	if (*str == ',')
 		++str;
@@ -307,7 +309,7 @@
 
 static bool __init swiotlb_default_size_changed(void)
 {
-	return default_nslabs != IO_TLB_DEFAULT_SIZE >> IO_TLB_SHIFT;
+	return swiotlb_size_set;
 }
 
 void __init swiotlb_adjust_size(unsigned long size)



  reply	other threads:[~2026-09-18  7:05 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-14  7:01 [PATCH v4 0/5] dma: swiotlb: Centralize default pool policy and sizing Aneesh Kumar K.V (Arm)
2026-09-14  7:01 ` [PATCH v4 1/5] dma: swiotlb: Centralize default pool policy selection Aneesh Kumar K.V (Arm)
2026-09-17 14:47   ` Catalin Marinas
2026-09-14  7:01 ` [PATCH v4 2/5] dma: swiotlb: Centralize minimal pool sizing Aneesh Kumar K.V (Arm)
2026-09-17 15:47   ` Catalin Marinas
2026-09-18  7:05     ` Aneesh Kumar K.V [this message]
2026-09-14  7:01 ` [PATCH v4 3/5] dma: swiotlb: Centralize memory-encryption " Aneesh Kumar K.V (Arm)
2026-09-17 16:02   ` Catalin Marinas
2026-09-18  7:13     ` Aneesh Kumar K.V
2026-09-14  7:01 ` [PATCH v4 4/5] dma: swiotlb: Add an overridable architecture pool opt-out Aneesh Kumar K.V (Arm)
2026-09-17 16:05   ` Catalin Marinas
2026-09-14  7:01 ` [PATCH v4 5/5] dma: swiotlb: Remove SWIOTLB_ANY Aneesh Kumar K.V (Arm)
2026-09-17 16:08   ` Catalin Marinas

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