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From: =?iso-8859-1?Q?M=E5ns_Rullg=E5rd?= <mans@mansr.com>
To: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: Julian Margetson <runaway@candw.ms>,
        Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
        Tejun Heo <tj@kernel.org>, linux-ide@vger.kernel.org,
        "linux-kernel\@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 1/3] ata: sata_dwc_460ex: use "dmas" DT property to find dma channel
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Date: Mon, 21 Dec 2015 18:25:31 +0000
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	(Andy Shevchenko's message of "Mon, 21 Dec 2015 19:55:53 +0200")
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Andy Shevchenko <andy.shevchenko@gmail.com> writes:

> On Mon, Dec 21, 2015 at 7:26 PM, Julian Margetson <runaway@candw.ms> wrote:
>> On 12/21/2015 12:48 PM, Andy Shevchenko wrote:
>>>
>>> On Sun, 2015-12-20 at 22:55 +0200, Andy Shevchenko wrote:
>>>>
>>>> On Sun, Dec 20, 2015 at 10:17 PM, Andy Shevchenko
>>>> <andy.shevchenko@gmail.com> wrote:
>>>>>
>>>>> On Sun, Dec 20, 2015 at 8:49 PM, Måns Rullgård <mans@mansr.com>
>>>>> wrote:
>>>>> I noticed thanks to DWC_PARAMS that burst size is hardcoded to 32
>>>>> items on this board, however registers for SATA program it to 64. I
>>>>> remember that I got no interrupt when I programmed transfer width
>>>>> wrongly (64 bits against 32 bits) when I ported dw_dmac to be used
>>>>> on
>>>>> Intel SoCs.
>>>>
>>>> One more thing, I have a patch to monitor DMA IO, we may check what
>>>> exactly the values are written / read  in DMA. I can share it
>>>> tomorrow.
>>>
>>> As promised the patch I have to debug IO of DW DMA. Didn't check though
>>> if it applies cleanly on top of recent vanilla kernel.
>
> So, the original driver (with patch from Måns) works, right?

Looks that way to me.  At least it's able to read the partition table.
What happens after that is hard to tell, but I don't see any obvious
errors.

-- 
Måns Rullgård