From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751661AbbLUVG2 (ORCPT ); Mon, 21 Dec 2015 16:06:28 -0500 Received: from unicorn.mansr.com ([81.2.72.234]:55111 "EHLO unicorn.mansr.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751013AbbLUVG0 convert rfc822-to-8bit (ORCPT ); Mon, 21 Dec 2015 16:06:26 -0500 From: =?iso-8859-1?Q?M=E5ns_Rullg=E5rd?= To: Andy Shevchenko Cc: Andy Shevchenko , Julian Margetson , Tejun Heo , linux-ide@vger.kernel.org, "linux-kernel\@vger.kernel.org" Subject: Re: [PATCH 1/3] ata: sata_dwc_460ex: use "dmas" DT property to find dma channel References: <1450221935-6034-1-git-send-email-mans@mansr.com> <56758F33.20804@candw.ms> <5675A84F.2070208@candw.ms> <5675BB2F.6060107@candw.ms> <5675C452.2080206@candw.ms> <5676E906.1060603@candw.ms> <1450724880.30729.250.camel@linux.intel.com> <1450731289.30729.282.camel@linux.intel.com> Date: Mon, 21 Dec 2015 21:06:23 +0000 In-Reply-To: <1450731289.30729.282.camel@linux.intel.com> (Andy Shevchenko's message of "Mon, 21 Dec 2015 22:54:49 +0200") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.5 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Andy Shevchenko writes: >> > 4. CHECK: PROTCTL bit (documentation says that recommended value is >> > 0x01) >> >> Any idea what the value of 0x3 used by the old sata driver means? >> Presumably that's decided by the bus. > > Nope, documentation says that it is direct representation of hprot[3:1] > wires on the master interface. Also it refers to AMBA spec, so, if you > have access to AMBA spec I think we might get it from there. That's assuming AMCC didn't change something. >> > 5. CHECK: Other bits in CFG register (FIFO_MODE, FCMODE) >> > 6. CHECK: Block interrupts vs. one interrupt at the end of block >> > chain >> > (Måns, I missed how any of them is ignored) >> >> The interrupt handler looks at the StatusTfr and StatusErr registers >> and ignores StatusBlock. > > I have to refresh my memory, since BLOCK interrupts should be enabled > (unmasked) separately. I have forgotten which type of interrupt is > generated in this case, BLOCK, or XFER after each block, or only one > XFER at the last block (LLP.LOC = 0) and BLOCK are ignored. So, will > check later. I interpreted the, admittedly a bit vague, documentation as meaning BLOCK interrupts are signalled after each block and XFER interrupts after the last block. >> > 7. AR: Test everything on Intel SoCs such as Baytrail, CherryTrail, >> > etc (SPI, UART, dmatest), AVR32 (MMC, dmatest), PPC 460EX (Onboard >> > SATA) >> >> I can test on AVR32.  That is as far as I know the only system I have >> with this DMA engine. > > If you have Intel Haswell, BayTrail, Braswell, CherryTrail, Broadwell, > you have it as well as long you have LPSS block there. (Most of them > are Atoms). I don't have any of those (or any Atom hardware). -- Måns Rullgård