From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760626AbcAKPJo (ORCPT ); Mon, 11 Jan 2016 10:09:44 -0500 Received: from unicorn.mansr.com ([81.2.72.234]:55944 "EHLO unicorn.mansr.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1760054AbcAKPJn convert rfc822-to-8bit (ORCPT ); Mon, 11 Jan 2016 10:09:43 -0500 From: =?iso-8859-1?Q?M=E5ns_Rullg=E5rd?= To: Andy Shevchenko Cc: Viresh Kumar , Dan Williams , Vinod Koul , dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 2/2] dmaengine: dw: fix cyclic transfer callbacks References: <1452517469-26922-1-git-send-email-mans@mansr.com> <1452517469-26922-3-git-send-email-mans@mansr.com> <1452524644.26146.34.camel@linux.intel.com> Date: Mon, 11 Jan 2016 15:09:39 +0000 In-Reply-To: <1452524644.26146.34.camel@linux.intel.com> (Andy Shevchenko's message of "Mon, 11 Jan 2016 17:04:04 +0200") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.5 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Andy Shevchenko writes: > On Mon, 2016-01-11 at 13:04 +0000, Mans Rullgard wrote: >> Cyclic transfer callbacks rely on block completion interrupts which >> were >> disabled in commit ff7b05f29fd4 ("dmaengine/dw_dmac: Don't handle >> block >> interrupts").  This re-enables block interrupts so the cyclic >> callbacks >> can work.  Other transfer types are not affected as they set the >> INT_EN >> bit only on the last block. >> >> Fixes: ff7b05f29fd4 ("dmaengine/dw_dmac: Don't handle block >> interrupts") >> Signed-off-by: Mans Rullgard > > How did you test that? With the ABDAC sound driver on the AVR32. It fails rather miserably without these patches. > From my understanding the custom stuff that does cyclic interrupts > prepares a set of descriptors per period, which at the end of transfer > will generate XFER interrupt. Next period will go in the same way. > > Maybe I missed something. The cyclic DMA is done by setting up a set of descriptors, one per period, with the last linked back to the first. The chain never ends, so there is never an XFER interrupt. -- Måns Rullgård