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Fri, 17 Jul 2026 09:22:54 -0700 (PDT) Date: Fri, 17 Jul 2026 11:22:40 -0500 From: Anirudh Srinivasan To: Klara Modin , Xu Lu Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, apw@canonical.com, joe@perches.com Subject: Re: [PATCH RESEND 1/2] riscv: mm: Apply svinval in update_mmu_cache() Message-ID: References: <20250901114141.5438-1-luxu.kernel@bytedance.com> <20250901114141.5438-2-luxu.kernel@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Wed, Jul 15, 2026 at 03:14:25AM +0200, Klara Modin wrote: > Hi, > > On 2025-09-01 19:41:40 +0800, Xu Lu wrote: > > Only flush tlb of the specified mm, and apply svinval if available. > > > > Signed-off-by: Xu Lu > > --- > > arch/riscv/include/asm/pgtable.h | 16 +++++++++++++++- > > arch/riscv/include/asm/tlbflush.h | 23 +++++++++++++++++++++++ > > arch/riscv/mm/tlbflush.c | 23 ----------------------- > > 3 files changed, 38 insertions(+), 24 deletions(-) > > > > diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h > > index 91697fbf1f901..165cd02d51629 100644 > > --- a/arch/riscv/include/asm/pgtable.h > > +++ b/arch/riscv/include/asm/pgtable.h > > @@ -495,9 +495,15 @@ static inline void update_mmu_cache_range(struct vm_fault *vmf, > > struct vm_area_struct *vma, unsigned long address, > > pte_t *ptep, unsigned int nr) > > { > > + int i; > > + unsigned long asid = get_mm_asid(vma->vm_mm); > > + > > asm goto(ALTERNATIVE("nop", "j %l[svvptc]", 0, RISCV_ISA_EXT_SVVPTC, 1) > > : : : : svvptc); > > > > + asm goto(ALTERNATIVE("nop", "j %l[svinval]", 0, RISCV_ISA_EXT_SVINVAL, 1) > > + : : : : svinval); > > + > > /* > > * The kernel assumes that TLBs don't cache invalid entries, but > > * in RISC-V, SFENCE.VMA specifies an ordering constraint, not a > > @@ -506,7 +512,15 @@ static inline void update_mmu_cache_range(struct vm_fault *vmf, > > * the extra traps reduce performance. So, eagerly SFENCE.VMA. > > */ > > while (nr--) > > - local_flush_tlb_page(address + nr * PAGE_SIZE); > > + local_flush_tlb_page_asid(address + nr * PAGE_SIZE, asid); > > + return; > > + > > +svinval: > > + local_sfence_w_inval(); > > > + for (i = 0; i < nr; i++) > > + local_sinval_vma(address + nr * PAGE_SIZE, asid); > > Probably should be > > + for (i = 0; i < nr; i++) > + local_sinval_vma(address + i * PAGE_SIZE, asid); > > instead. My BPI-f3 hangs when entering the initramfs with the original > patch. Reverting also fixes it. I'm also noticing this. linux-next is unable to enter userspace due to this on Spacemit K1. Hopefully we can get a fix merged in soon. Regards Anirudh Srinivasan > > > + local_sfence_inval_ir(); > > + return; > > > > svvptc:; > > /* > > Regards, > Klara Modin > > ...