Re: [PATCH] clk: meson: g12a: fix gp0 and hifi ranges

[Neil Armstrong <narmstrong@baylibre.com>]

On 25/03/2019 13:18, Neil Armstrong wrote:
> On 25/03/2019 11:42, Jerome Brunet wrote:
>> While some SoC samples are able to lock with a PLL factor of 55, others
>> samples can't. ATM, a minimum of 60 appears to work on all the samples
>> I have tried, so lets use this value until we have a good reason to put
>> something else.
>>
>> Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller")
>> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
>> ---
>>  drivers/clk/meson/g12a.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
>> index 0e1ce8c03259..d3f53a9b97dc 100644
>> --- a/drivers/clk/meson/g12a.c
>> +++ b/drivers/clk/meson/g12a.c
>> @@ -151,7 +151,7 @@ static struct clk_regmap g12a_sys_pll = {
>>  };
>>  
>>  static const struct pll_mult_range g12a_gp0_pll_mult_range = {
>> -	.min = 55,
>> +	.min = 60,
>>  	.max = 255,
>>  };
>>  
>>
> 
> Acked-by: Neil Armstrong <narmstrong@baylibre.com>
> 
> And applied to fixes/drivers !
> 
> Neil
> 

Seems this will need more work,
unapplied from fixes/drivers

Neil

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