From: Neil Armstrong <narmstrong@baylibre.com>
To: Jerome Brunet <jbrunet@baylibre.com>
Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] clk: meson: g12a: fix gp0 and hifi ranges
Date: Mon, 25 Mar 2019 13:18:59 +0100 [thread overview]
Message-ID: <823ef5d3-3da8-2be0-5bef-ed9b601d287b@baylibre.com> (raw)
In-Reply-To: <20190325104230.11245-1-jbrunet@baylibre.com>
On 25/03/2019 11:42, Jerome Brunet wrote:
> While some SoC samples are able to lock with a PLL factor of 55, others
> samples can't. ATM, a minimum of 60 appears to work on all the samples
> I have tried, so lets use this value until we have a good reason to put
> something else.
>
> Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller")
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
> ---
> drivers/clk/meson/g12a.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
> index 0e1ce8c03259..d3f53a9b97dc 100644
> --- a/drivers/clk/meson/g12a.c
> +++ b/drivers/clk/meson/g12a.c
> @@ -151,7 +151,7 @@ static struct clk_regmap g12a_sys_pll = {
> };
>
> static const struct pll_mult_range g12a_gp0_pll_mult_range = {
> - .min = 55,
> + .min = 60,
> .max = 255,
> };
>
>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
And applied to fixes/drivers !
Neil
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next prev parent reply other threads:[~2019-03-25 12:19 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-25 10:42 Jerome Brunet
2019-03-25 12:18 ` Neil Armstrong [this message]
2019-03-29 8:39 ` Neil Armstrong
2021-04-29 9:03 Jerome Brunet
2021-04-29 9:20 ` Neil Armstrong
2021-04-29 9:45 ` Jerome Brunet
2021-04-29 12:15 ` Neil Armstrong
2021-04-29 12:16 ` Jerome Brunet
2021-05-20 14:02 ` Neil Armstrong
2021-05-24 9:38 ` Jerome Brunet
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