[PATCH v1 0/3] clk: meson: small fixes for HDMI PLL OD

[PATCH v1 0/3] clk: meson: small fixes for HDMI PLL OD

[Martin Blumenstingl]

Hi Jerome,

this series contains two fixes for preventing HDMI PLL OD /8 on
GXL/GXM and G12A/G12B/SM1, like the downstream driver does. See:
- downstream GXBB code: [0]
- downstream GXL/GXM code: [1]
- downstream G12A/G12B/SM1 code: [2]

I have verified this on GXL (Le Potato) by setting HDMI PLL OD1 to 0x3
(which should result in divide-by-8). The resulting frequency reported
by meson-clk-msr is double (meaning: only divide-by-4) compared to what
CCF sees.

These are not critical for now since the CCF code-path for the HDMI PLL
is read-only (as drm/meson directly programs the registers).

Additionally there's a cosmetic fix to use the HHI_HDMI_PLL_CNTL3 macro
instead of calculating HHI_HDMI_PLL_CNTL + 8.


[0] https://github.com/hardkernel/linux/blob/0e658067af67835a625e41e289effc4ee390d62f/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c#L505-L627
[1] https://github.com/hardkernel/linux/blob/0e658067af67835a625e41e289effc4ee390d62f/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_gxl.c#L501-L553
[2] https://github.com/hardkernel/linux/blob/0e658067af67835a625e41e289effc4ee390d62f/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c#L671-L721


Martin Blumenstingl (3):
  clk: meson: gxbb: Limit the HDMI PLL OD to /4 on GXL/GXM SoCs
  clk: meson: g12a: Limit the HDMI PLL OD to /4
  clk: meson: gxbb: use the existing HHI_HDMI_PLL_CNTL3 macro

 drivers/clk/meson/g12a.c | 13 ++++++++++---
 drivers/clk/meson/gxbb.c | 19 +++++++++++++------
 2 files changed, 23 insertions(+), 9 deletions(-)

-- 
2.52.0


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[PATCH v1 1/3] clk: meson: gxbb: Limit the HDMI PLL OD to /4 on GXL/GXM SoCs

[Martin Blumenstingl]

GXBB has the HDMI PLL OD in the HHI_HDMI_PLL_CNTL2 register while for
GXL/GXM the OD has moved to HHI_HDMI_PLL_CNTL3. At first glance the rest
of the OD setup seems identical.

However, looking at the downstream kernel sources as well as testing
shows that GXL only supports three OD values:
- register value 0 means: divide by 1
- register value 1 means: divide by 2
- register value 2 means: divide by 4

Using register value 3 (which on GXBB means: divide by 8) still divides
by 4 as verified using meson-clk-measure. Downstream sources are also
only using OD register values 0, 1 and 2 for GXL (while for GXBB the
downstream kernel sources are also using value 3).

Add clk_div_table and have it replace the CLK_DIVIDER_POWER_OF_TWO flag
to make the kernel's view of this register match with how the hardware
actually works.

Fixes: 69d92293274b ("clk: meson: add the gxl hdmi pll")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 drivers/clk/meson/gxbb.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 5a229c4ffae1..0788b9b1ed21 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -349,12 +349,19 @@ static struct clk_regmap gxbb_hdmi_pll = {
 	},
 };
 
+static const struct clk_div_table gxl_hdmi_pll_od_div_table[] = {
+	{ .val = 0, .div = 1 },
+	{ .val = 1, .div = 2 },
+	{ .val = 2, .div = 4 },
+	{ /* sentinel */ }
+};
+
 static struct clk_regmap gxl_hdmi_pll_od = {
 	.data = &(struct clk_regmap_div_data){
 		.offset = HHI_HDMI_PLL_CNTL + 8,
 		.shift = 21,
 		.width = 2,
-		.flags = CLK_DIVIDER_POWER_OF_TWO,
+		.table = gxl_hdmi_pll_od_div_table,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "hdmi_pll_od",
@@ -372,7 +379,7 @@ static struct clk_regmap gxl_hdmi_pll_od2 = {
 		.offset = HHI_HDMI_PLL_CNTL + 8,
 		.shift = 23,
 		.width = 2,
-		.flags = CLK_DIVIDER_POWER_OF_TWO,
+		.table = gxl_hdmi_pll_od_div_table,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "hdmi_pll_od2",
@@ -390,7 +397,7 @@ static struct clk_regmap gxl_hdmi_pll = {
 		.offset = HHI_HDMI_PLL_CNTL + 8,
 		.shift = 19,
 		.width = 2,
-		.flags = CLK_DIVIDER_POWER_OF_TWO,
+		.table = gxl_hdmi_pll_od_div_table,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "hdmi_pll",
-- 
2.52.0


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[PATCH v1 2/3] clk: meson: g12a: Limit the HDMI PLL OD to /4

[Martin Blumenstingl]

GXBB has the HDMI PLL OD in the HHI_HDMI_PLL_CNTL2 register while for
G12A/G12B/SM1 the OD has moved to HHI_HDMI_PLL_CNTL0. At first glance
the rest of the OD setup seems identical.

However, looking at the downstream kernel sources as well as testing
shows that G12A/G12B/SM1 only supports three OD values:
- register value 0 means: divide by 1
- register value 1 means: divide by 2
- register value 2 means: divide by 4

Downstream sources are also only using OD register values 0, 1 and 2
for G12A/G12B/SM1 (while for GXBB the downstream kernel sources are also
using value 3 which means: divide by 8).

Add clk_div_table and have it replace the CLK_DIVIDER_POWER_OF_TWO flag
to make the kernel's view of this register match with how the hardware
actually works.

Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 drivers/clk/meson/g12a.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index 185b6348251d..19057d2dff47 100644
--- a/drivers/clk/meson/g12a.c
+++ b/drivers/clk/meson/g12a.c
@@ -777,12 +777,19 @@ static struct clk_regmap g12a_hdmi_pll_dco = {
 	},
 };
 
+static const struct clk_div_table g12a_hdmi_pll_od_div_table[] = {
+	{ .val = 0, .div = 1 },
+	{ .val = 1, .div = 2 },
+	{ .val = 2, .div = 4 },
+	{ /* sentinel */ }
+};
+
 static struct clk_regmap g12a_hdmi_pll_od = {
 	.data = &(struct clk_regmap_div_data){
 		.offset = HHI_HDMI_PLL_CNTL0,
 		.shift = 16,
 		.width = 2,
-		.flags = CLK_DIVIDER_POWER_OF_TWO,
+		.table = g12a_hdmi_pll_od_div_table,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "hdmi_pll_od",
@@ -800,7 +807,7 @@ static struct clk_regmap g12a_hdmi_pll_od2 = {
 		.offset = HHI_HDMI_PLL_CNTL0,
 		.shift = 18,
 		.width = 2,
-		.flags = CLK_DIVIDER_POWER_OF_TWO,
+		.table = g12a_hdmi_pll_od_div_table,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "hdmi_pll_od2",
@@ -818,7 +825,7 @@ static struct clk_regmap g12a_hdmi_pll = {
 		.offset = HHI_HDMI_PLL_CNTL0,
 		.shift = 20,
 		.width = 2,
-		.flags = CLK_DIVIDER_POWER_OF_TWO,
+		.table = g12a_hdmi_pll_od_div_table,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "hdmi_pll",
-- 
2.52.0


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[PATCH v1 3/3] clk: meson: gxbb: use the existing HHI_HDMI_PLL_CNTL3 macro

[Martin Blumenstingl]

There's no need to calculate HHI_HDMI_PLL_CNTL + 8 when we have a
HHI_HDMI_PLL_CNTL3 macro that has the correct offset already. No
functional changes, this makes it easier to compare the driver with the
datasheets.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 drivers/clk/meson/gxbb.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 0788b9b1ed21..0900f4e44764 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -358,7 +358,7 @@ static const struct clk_div_table gxl_hdmi_pll_od_div_table[] = {
 
 static struct clk_regmap gxl_hdmi_pll_od = {
 	.data = &(struct clk_regmap_div_data){
-		.offset = HHI_HDMI_PLL_CNTL + 8,
+		.offset = HHI_HDMI_PLL_CNTL3,
 		.shift = 21,
 		.width = 2,
 		.table = gxl_hdmi_pll_od_div_table,
@@ -376,7 +376,7 @@ static struct clk_regmap gxl_hdmi_pll_od = {
 
 static struct clk_regmap gxl_hdmi_pll_od2 = {
 	.data = &(struct clk_regmap_div_data){
-		.offset = HHI_HDMI_PLL_CNTL + 8,
+		.offset = HHI_HDMI_PLL_CNTL3,
 		.shift = 23,
 		.width = 2,
 		.table = gxl_hdmi_pll_od_div_table,
@@ -394,7 +394,7 @@ static struct clk_regmap gxl_hdmi_pll_od2 = {
 
 static struct clk_regmap gxl_hdmi_pll = {
 	.data = &(struct clk_regmap_div_data){
-		.offset = HHI_HDMI_PLL_CNTL + 8,
+		.offset = HHI_HDMI_PLL_CNTL3,
 		.shift = 19,
 		.width = 2,
 		.table = gxl_hdmi_pll_od_div_table,
-- 
2.52.0


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Re: [PATCH v1 0/3] clk: meson: small fixes for HDMI PLL OD

[Jerome Brunet]

On lun. 05 janv. 2026 at 21:47, Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote:

> Hi Jerome,
>
> this series contains two fixes for preventing HDMI PLL OD /8 on
> GXL/GXM and G12A/G12B/SM1, like the downstream driver does. See:
> - downstream GXBB code: [0]
> - downstream GXL/GXM code: [1]
> - downstream G12A/G12B/SM1 code: [2]
>
> I have verified this on GXL (Le Potato) by setting HDMI PLL OD1 to 0x3
> (which should result in divide-by-8). The resulting frequency reported
> by meson-clk-msr is double (meaning: only divide-by-4) compared to what
> CCF sees.
>
> These are not critical for now since the CCF code-path for the HDMI PLL
> is read-only (as drm/meson directly programs the registers).
>
> Additionally there's a cosmetic fix to use the HHI_HDMI_PLL_CNTL3 macro
> instead of calculating HHI_HDMI_PLL_CNTL + 8.
>
>
> [0] https://github.com/hardkernel/linux/blob/0e658067af67835a625e41e289effc4ee390d62f/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c#L505-L627
> [1] https://github.com/hardkernel/linux/blob/0e658067af67835a625e41e289effc4ee390d62f/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_gxl.c#L501-L553
> [2] https://github.com/hardkernel/linux/blob/0e658067af67835a625e41e289effc4ee390d62f/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c#L671-L721
>
>
> Martin Blumenstingl (3):
>   clk: meson: gxbb: Limit the HDMI PLL OD to /4 on GXL/GXM SoCs
>   clk: meson: g12a: Limit the HDMI PLL OD to /4
>   clk: meson: gxbb: use the existing HHI_HDMI_PLL_CNTL3 macro

Looks good.

I'd like to add a comment like this in the code

+/*
+ * GXL hdmi OD dividers are POWER_OF_TWO dividers but limited to /4.
+ * A divider value of 3 should map to /8 but instead map /4 so ignore it.
+ */

(and a similar one for the G12). Is this Ok with you ?

>
>  drivers/clk/meson/g12a.c | 13 ++++++++++---
>  drivers/clk/meson/gxbb.c | 19 +++++++++++++------
>  2 files changed, 23 insertions(+), 9 deletions(-)

-- 
Jerome

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Re: [PATCH v1 0/3] clk: meson: small fixes for HDMI PLL OD

[Martin Blumenstingl]

Hi Jerome,

On Tue, Jan 6, 2026 at 11:25 AM Jerome Brunet <jbrunet@baylibre.com> wrote:
[...]
> > Martin Blumenstingl (3):
> >   clk: meson: gxbb: Limit the HDMI PLL OD to /4 on GXL/GXM SoCs
> >   clk: meson: g12a: Limit the HDMI PLL OD to /4
> >   clk: meson: gxbb: use the existing HHI_HDMI_PLL_CNTL3 macro
>
> Looks good.
>
> I'd like to add a comment like this in the code
>
> +/*
> + * GXL hdmi OD dividers are POWER_OF_TWO dividers but limited to /4.
> + * A divider value of 3 should map to /8 but instead map /4 so ignore it.
> + */
>
> (and a similar one for the G12). Is this Ok with you ?
Sure, I'm happy to either have you add the comment when applying or me
doing it and sending a v2 - whichever you prefer.

Best regards,
Martin

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Re: [PATCH v1 0/3] clk: meson: small fixes for HDMI PLL OD

[Jerome Brunet]

Applied to clk-meson (clk-meson-next), thanks!

[1/3] clk: meson: gxbb: Limit the HDMI PLL OD to /4 on GXL/GXM SoCs
      https://github.com/BayLibre/clk-meson/commit/5b1a43950fd3
[2/3] clk: meson: g12a: Limit the HDMI PLL OD to /4
      https://github.com/BayLibre/clk-meson/commit/7aa6c24697ef
[3/3] clk: meson: gxbb: use the existing HHI_HDMI_PLL_CNTL3 macro
      https://github.com/BayLibre/clk-meson/commit/2fe1ef40b58c

Best regards,
--
Jerome

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