[PATCH net] net: mdio-mux-meson-gxl: set RESERVED0 bit in REG2

[PATCH net] net: mdio-mux-meson-gxl: set RESERVED0 bit in REG2

[Da Xue]

The first RESERVED register bit needs to be set in order for the PHY
to come up. Otherwise the ethernet device stays in "No Carrier".
There's no associated documentation for this register bit in the
Amlogic datasheets, only the default value to set for the entire
register.

This register bit is normally set in u-boot so it is not noticed in
Linux. During my testing with u-boot net disabled, this problem crops
up.

Signed-off-by: Da Xue <da@libre.computer>
---
 drivers/net/mdio/mdio-mux-meson-gxl.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/net/mdio/mdio-mux-meson-gxl.c
b/drivers/net/mdio/mdio-mux-meson-gxl.c
index 76188575ca1f..210a52d98112 100644
--- a/drivers/net/mdio/mdio-mux-meson-gxl.c
+++ b/drivers/net/mdio/mdio-mux-meson-gxl.c
@@ -17,6 +17,7 @@
 #define  REG2_LEDACT           GENMASK(23, 22)
 #define  REG2_LEDLINK          GENMASK(25, 24)
 #define  REG2_DIV4SEL          BIT(27)
+#define  REG2_RESERVED0                BIT(28)
 #define  REG2_ADCBYPASS                BIT(30)
 #define  REG2_CLKINSEL         BIT(31)
 #define ETH_REG3               0x4
@@ -65,7 +66,7 @@ static void gxl_enable_internal_mdio(struct
gxl_mdio_mux *priv)
         * The only constraint is that it must match the one in
         * drivers/net/phy/meson-gxl.c to properly match the PHY.
         */
-       writel(FIELD_PREP(REG2_PHYID, EPHY_GXL_ID),
+       writel(REG2_RESERVED0 | FIELD_PREP(REG2_PHYID, EPHY_GXL_ID),
               priv->regs + ETH_REG2);

        /* Enable the internal phy */
-- 
2.39.2

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Re: [PATCH net] net: mdio-mux-meson-gxl: set RESERVED0 bit in REG2

[Jerome Brunet]

On Tue 01 Aug 2023 at 16:34, Da Xue <da@libre.computer> wrote:

> The first RESERVED register bit needs to be set in order for the PHY
> to come up. Otherwise the ethernet device stays in "No Carrier".
> There's no associated documentation for this register bit in the
> Amlogic datasheets, only the default value to set for the entire
> register.
>
> This register bit is normally set in u-boot so it is not noticed in
> Linux. During my testing with u-boot net disabled, this problem crops
> up.
>
> Signed-off-by: Da Xue <da@libre.computer>

Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>

> ---
>  drivers/net/mdio/mdio-mux-meson-gxl.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/mdio/mdio-mux-meson-gxl.c
> b/drivers/net/mdio/mdio-mux-meson-gxl.c
> index 76188575ca1f..210a52d98112 100644
> --- a/drivers/net/mdio/mdio-mux-meson-gxl.c
> +++ b/drivers/net/mdio/mdio-mux-meson-gxl.c
> @@ -17,6 +17,7 @@
>  #define  REG2_LEDACT           GENMASK(23, 22)
>  #define  REG2_LEDLINK          GENMASK(25, 24)
>  #define  REG2_DIV4SEL          BIT(27)
> +#define  REG2_RESERVED0                BIT(28)
>  #define  REG2_ADCBYPASS                BIT(30)
>  #define  REG2_CLKINSEL         BIT(31)
>  #define ETH_REG3               0x4
> @@ -65,7 +66,7 @@ static void gxl_enable_internal_mdio(struct
> gxl_mdio_mux *priv)
>          * The only constraint is that it must match the one in
>          * drivers/net/phy/meson-gxl.c to properly match the PHY.
>          */
> -       writel(FIELD_PREP(REG2_PHYID, EPHY_GXL_ID),
> +       writel(REG2_RESERVED0 | FIELD_PREP(REG2_PHYID, EPHY_GXL_ID),
>                priv->regs + ETH_REG2);
>
>         /* Enable the internal phy */


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