From: jbrunet@baylibre.com (Jerome Brunet)
To: linus-amlogic@lists.infradead.org
Subject: [PATCH 7/7] dt-bindings: clk: gxbb: expose i2s output clock gates
Date: Tue, 28 Feb 2017 14:30:02 +0100 [thread overview]
Message-ID: <20170228133002.17894-8-jbrunet@baylibre.com> (raw)
In-Reply-To: <20170228133002.17894-1-jbrunet@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
drivers/clk/meson/gxbb.h | 10 +++++-----
include/dt-bindings/clock/gxbb-clkc.h | 5 +++++
2 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index dc487180f847..95a83b7709ca 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -206,16 +206,16 @@
#define CLKID_I2S_SPDIF 35
#define CLKID_ETH 36
#define CLKID_DEMUX 37
-#define CLKID_AIU_GLUE 38
+/* CLKID_AIU_GLUE */
#define CLKID_IEC958 39
-#define CLKID_I2S_OUT 40
+/* CLKID_I2S_OUT */
#define CLKID_AMCLK 41
#define CLKID_AIFIFO2 42
#define CLKID_MIXER 43
-#define CLKID_MIXER_IFACE 44
+/* CLKID_MIXER_IFACE */
#define CLKID_ADC 45
#define CLKID_BLKMV 46
-#define CLKID_AIU 47
+/* CLKID_AIU */
#define CLKID_UART1 48
#define CLKID_G2D 49
/* CLKID_USB0 */
@@ -248,7 +248,7 @@
/* CLKID_GCLK_VENCI_INT0 */
#define CLKID_GCLK_VENCI_INT 78
#define CLKID_DAC_CLK 79
-#define CLKID_AOCLK_GATE 80
+/* CLKID_AOCLK_GATE */
#define CLKID_IEC958_GATE 81
#define CLKID_ENC480P 82
#define CLKID_RNG1 83
diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
index 692846c7941b..f08f06dd7702 100644
--- a/include/dt-bindings/clock/gxbb-clkc.h
+++ b/include/dt-bindings/clock/gxbb-clkc.h
@@ -16,6 +16,10 @@
#define CLKID_I2C 22
#define CLKID_SAR_ADC 23
#define CLKID_ETH 36
+#define CLKID_AIU_GLUE 38
+#define CLKID_I2S_OUT 40
+#define CLKID_MIXER_IFACE 44
+#define CLKID_AIU 47
#define CLKID_USB0 50
#define CLKID_USB1 51
#define CLKID_USB 55
@@ -24,6 +28,7 @@
#define CLKID_USB0_DDR_BRIDGE 65
#define CLKID_SANA 69
#define CLKID_GCLK_VENCI_INT0 77
+#define CLKID_AOCLK_GATE 80
#define CLKID_AO_I2C 93
#define CLKID_SD_EMMC_A 94
#define CLKID_SD_EMMC_B 95
--
2.9.3
prev parent reply other threads:[~2017-02-28 13:30 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-28 13:29 [PATCH 0/7] clk: meson: update clock controller for audio support Jerome Brunet
2017-02-28 13:29 ` [PATCH 1/7] clk: meson8b: put dividers and muxes in tables Jerome Brunet
2017-02-28 13:29 ` [PATCH 2/7] clk: gxbb: " Jerome Brunet
2017-02-28 13:29 ` [PATCH 3/7] clk: meson: mpll: add rw operation Jerome Brunet
2017-02-28 13:29 ` [PATCH 4/7] clk: meson: gxbb: mpll: use " Jerome Brunet
2017-02-28 13:30 ` [PATCH 5/7] clk: meson8b: add the mplls clocks 0, 1 and 2 Jerome Brunet
2017-02-28 13:30 ` [PATCH 6/7] clk: meson: mpll: correct N2 maximum value Jerome Brunet
2017-02-28 13:30 ` Jerome Brunet [this message]
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