From: jbrunet@baylibre.com (Jerome Brunet)
To: linus-amlogic@lists.infradead.org
Subject: [PATCH 05/11] clk: meson: add gp0 frac parameter for axg and gxl
Date: Mon, 19 Feb 2018 12:21:40 +0100 [thread overview]
Message-ID: <20180219112146.21746-6-jbrunet@baylibre.com> (raw)
In-Reply-To: <20180219112146.21746-1-jbrunet@baylibre.com>
Add the frac parameter for the gp0 pll of the axg and gxl.
This allows to achieve rates between the fixed settings provided
by the table.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
drivers/clk/meson/axg.c | 7 ++++++-
drivers/clk/meson/gxbb.c | 7 ++++++-
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index 4f13929cd594..892572a2d70f 100644
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -193,7 +193,7 @@ static const struct pll_rate_table axg_gp0_pll_rate_table[] = {
};
const struct reg_sequence axg_gp0_init_regs[] = {
- { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084a000 },
+ { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 },
{ .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be },
{ .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 },
{ .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d },
@@ -218,6 +218,11 @@ static struct clk_regmap axg_gp0_pll = {
.shift = 16,
.width = 2,
},
+ .frac = {
+ .reg_off = HHI_GP0_PLL_CNTL1,
+ .shift = 0,
+ .width = 10,
+ },
.l = {
.reg_off = HHI_GP0_PLL_CNTL,
.shift = 31,
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index ac48eef0f490..fdeb372863de 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -437,7 +437,7 @@ static struct clk_regmap gxbb_gp0_pll = {
};
const struct reg_sequence gxl_gp0_init_regs[] = {
- { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084a000 },
+ { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 },
{ .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be },
{ .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 },
{ .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d },
@@ -462,6 +462,11 @@ static struct clk_regmap gxl_gp0_pll = {
.shift = 16,
.width = 2,
},
+ .frac = {
+ .reg_off = HHI_GP0_PLL_CNTL1,
+ .shift = 0,
+ .width = 10,
+ },
.l = {
.reg_off = HHI_GP0_PLL_CNTL,
.shift = 31,
--
2.14.3
next prev parent reply other threads:[~2018-02-19 11:21 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-19 11:21 [PATCH 00/11] clk: meson: second round of updates Jerome Brunet
2018-02-19 11:21 ` [PATCH 01/11] clk: meson: add fractional part of meson8b fixed_pll Jerome Brunet
2018-02-19 11:21 ` [PATCH 02/11] clk: meson: poke pll CNTL last Jerome Brunet
2018-02-19 11:21 ` [PATCH 03/11] clk: meson: remove special gp0 lock loop Jerome Brunet
2018-02-19 11:21 ` [PATCH 04/11] clk: meson: improve pll driver results with frac Jerome Brunet
2018-02-19 11:21 ` Jerome Brunet [this message]
2018-02-19 11:21 ` [PATCH 06/11] clk: meson: add ROUND_CLOSEST to the pll driver Jerome Brunet
2018-02-19 11:21 ` [PATCH 07/11] clk: meson: axg: add hifi clock bindings Jerome Brunet
2018-02-19 11:21 ` [PATCH 08/11] clk: meson: axg: add hifi pll clock Jerome Brunet
2018-02-19 11:21 ` [PATCH 09/11] clk: meson: add mpll pre-divider Jerome Brunet
2018-02-19 11:21 ` [PATCH 10/11] clk: meson: add fdiv clock gates Jerome Brunet
2018-02-19 11:21 ` [PATCH 11/11] clk: meson: clean-up clk81 clocks Jerome Brunet
2018-03-12 10:22 ` [PATCH 00/11] clk: meson: second round of updates Neil Armstrong
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