From: jbrunet@baylibre.com (Jerome Brunet)
To: linus-amlogic@lists.infradead.org
Subject: [PATCH 06/11] clk: meson: add ROUND_CLOSEST to the pll driver
Date: Mon, 19 Feb 2018 12:21:41 +0100 [thread overview]
Message-ID: <20180219112146.21746-7-jbrunet@baylibre.com> (raw)
In-Reply-To: <20180219112146.21746-1-jbrunet@baylibre.com>
Provide an option for the pll driver to round to the rate closest to the
requested rate, instead of systematically rounding down.
This may allow the provided rate to be closer to the requested rate when
rounding up is not an issue
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
drivers/clk/meson/clk-pll.c | 17 +++++++++++++----
drivers/clk/meson/clkc.h | 2 ++
2 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
index d58961f35b71..65a7bd903551 100644
--- a/drivers/clk/meson/clk-pll.c
+++ b/drivers/clk/meson/clk-pll.c
@@ -105,7 +105,12 @@ static u16 __pll_params_with_frac(unsigned long rate,
u64 val = (u64)rate * pllt->n;
val <<= pllt->od + pllt->od2 + pllt->od3;
- val = div_u64(val * frac_max, parent_rate);
+
+ if (pll->flags & CLK_MESON_PLL_ROUND_CLOSEST)
+ val = DIV_ROUND_CLOSEST_ULL(val * frac_max, parent_rate);
+ else
+ val = div_u64(val * frac_max, parent_rate);
+
val -= pllt->m * frac_max;
return min((u16)val, (u16)(frac_max - 1));
@@ -125,9 +130,13 @@ meson_clk_get_pll_settings(unsigned long rate,
while (table[i].rate && table[i].rate <= rate)
i++;
- /* Select the setting of the rounded down rate */
- if (i != 0)
- i--;
+ if (i != 0) {
+ if (MESON_PARM_APPLICABLE(&pll->frac) ||
+ !(pll->flags & CLK_MESON_PLL_ROUND_CLOSEST) ||
+ (abs(rate - table[i - 1].rate) <
+ abs(rate - table[i].rate)))
+ i--;
+ }
return (struct pll_rate_table *)&table[i];
}
diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h
index 9cdcd9b6c16c..8fe73c4edca8 100644
--- a/drivers/clk/meson/clkc.h
+++ b/drivers/clk/meson/clkc.h
@@ -71,6 +71,8 @@ struct pll_rate_table {
.od = (_od), \
}
+#define CLK_MESON_PLL_ROUND_CLOSEST BIT(0)
+
struct meson_clk_pll_data {
struct parm m;
struct parm n;
--
2.14.3
next prev parent reply other threads:[~2018-02-19 11:21 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-19 11:21 [PATCH 00/11] clk: meson: second round of updates Jerome Brunet
2018-02-19 11:21 ` [PATCH 01/11] clk: meson: add fractional part of meson8b fixed_pll Jerome Brunet
2018-02-19 11:21 ` [PATCH 02/11] clk: meson: poke pll CNTL last Jerome Brunet
2018-02-19 11:21 ` [PATCH 03/11] clk: meson: remove special gp0 lock loop Jerome Brunet
2018-02-19 11:21 ` [PATCH 04/11] clk: meson: improve pll driver results with frac Jerome Brunet
2018-02-19 11:21 ` [PATCH 05/11] clk: meson: add gp0 frac parameter for axg and gxl Jerome Brunet
2018-02-19 11:21 ` Jerome Brunet [this message]
2018-02-19 11:21 ` [PATCH 07/11] clk: meson: axg: add hifi clock bindings Jerome Brunet
2018-02-19 11:21 ` [PATCH 08/11] clk: meson: axg: add hifi pll clock Jerome Brunet
2018-02-19 11:21 ` [PATCH 09/11] clk: meson: add mpll pre-divider Jerome Brunet
2018-02-19 11:21 ` [PATCH 10/11] clk: meson: add fdiv clock gates Jerome Brunet
2018-02-19 11:21 ` [PATCH 11/11] clk: meson: clean-up clk81 clocks Jerome Brunet
2018-03-12 10:22 ` [PATCH 00/11] clk: meson: second round of updates Neil Armstrong
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