[PATCH 0/2] PCI: dwc: Clean up DWC PCIe register macros

[PATCH 0/2] PCI: dwc: Clean up DWC PCIe register macros

[Hans Zhang]

This series cleans up the DWC PCIe controller register macros to better
match the Synopsys DesignWare PCIe Controller Reference Manual, and
removes an unused set of iATU unroll register definitions.

Patch 1 renames various register and field macros, dropping redundant
PCIE_ prefixes and using documented base names.  Field macros are
renamed consistently so their register association is clear.  No
functional change intended.

Patch 2 removes the unused PCIE_ATU_UNR_* macros.  These have no
remaining users now that the driver uses the ATU_* macros and
ATU_UNROLL_BASE() for unrolled iATU register access.

The series was build-tested with defconfig and allmodconfig.

---
Changes in v2:
- Rename Port Link Control register to PORT_LINK_CTRL instead of
  PORT_LINK_CTRL_OFF, as suggested by Bjorn.  The _OFF suffix is
  ambiguous and unnecessary.
- Extend the cleanup to more DWC PCIe register macros, dropping the
  redundant PCIE_ prefix and using documented base names, such as
  PORT_FORCE_LINK, PORT_AFAC, PORT_LANE_SKEW, TIMER_CTRL_MAX_FUNC_NUM,
  PORT_LINK_DEBUG0/1, LINK_WIDTH_SPEED_CTRL, GEN3_CTRL, GEN3_EQ_CTRL,
  MULTI_LANE_CTRL, MISC_CONTROL_1, MSIX_DOORBELL, and the ATU_*
  registers.
- Include the register name in field macros, e.g. PORT_LINK_CTRL_DLE,
  PORT_LINK_CTRL_FLM, PORT_LINK_CTRL_LC_*.
- Fix PORT_AFAC L1 field names (PORT_AFAC_L1_*).
- Unify COHERENCY_CTRL1/2/3 and RAS_DES_EVENT_COUNTER_* naming.
- Drop the _OFF suffix from MISC_CONTROL_1.
- Add a patch to remove unused PCIE_ATU_UNR_* definitions.

v1:
https://patchwork.kernel.org/project/linux-pci/patch/20260904061823.592216-1-18255117159@163.com/
---

Hans Zhang (2):
  PCI: dwc: Align register macros with Synopsys documentation
  PCI: dwc: Remove unused PCIE_ATU_UNR_* register definitions

 drivers/pci/controller/dwc/pci-imx6.c         |  26 +-
 drivers/pci/controller/dwc/pci-keystone.c     |   4 +-
 .../pci/controller/dwc/pcie-designware-ep.c   |  10 +-
 .../pci/controller/dwc/pcie-designware-host.c |  18 +-
 drivers/pci/controller/dwc/pcie-designware.c  | 176 +++++------
 drivers/pci/controller/dwc/pcie-designware.h  | 275 +++++++++---------
 drivers/pci/controller/dwc/pcie-fu740.c       |   6 +-
 drivers/pci/controller/dwc/pcie-nxp-s32g.c    |  18 +-
 drivers/pci/controller/dwc/pcie-qcom-common.c |  28 +-
 drivers/pci/controller/dwc/pcie-qcom.c        |   6 +-
 drivers/pci/controller/dwc/pcie-rcar-gen4.c   |  26 +-
 .../pci/controller/dwc/pcie-tegra194-acpi.c   |  22 +-
 drivers/pci/controller/dwc/pcie-tegra194.c    |  86 +++---
 drivers/pci/controller/dwc/pcie-ultrarisc.c   |  10 +-
 14 files changed, 349 insertions(+), 362 deletions(-)


base-commit: 08df884136f1c1197bab2a27814404fd329d9aac
-- 
2.34.1


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[PATCH 1/2] PCI: dwc: Align register macros with Synopsys documentation

[Hans Zhang]

The DWC PCIe register and field macros are inconsistently named and
often do not match the Synopsys DesignWare PCIe Controller Reference
Manual.  This makes it harder to cross-reference the code with the
documentation when debugging or maintaining the driver.

As suggested during review, do not add an "_OFF" suffix to the Port Link
Control register: the suffix is ambiguous (offset vs. off) and
unnecessary.  Use PORT_LINK_CTRL, and include the register name in its
field macros, e.g. PORT_LINK_CTRL_DLE, PORT_LINK_CTRL_FLM, and
PORT_LINK_CTRL_LC_*.

Align other DWC PCIe controller-internal register macros in the same
spirit by dropping the redundant PCIE_ prefix and using the documented
base names, such as PORT_FORCE_LINK, PORT_AFAC, PORT_LANE_SKEW,
TIMER_CTRL_MAX_FUNC_NUM, PORT_LINK_DEBUG0/1, LINK_WIDTH_SPEED_CTRL,
GEN3_CTRL, GEN3_EQ_CTRL, MULTI_LANE_CTRL, MISC_CONTROL_1,
MSIX_DOORBELL, and the ATU_* registers.  Field macros are renamed
consistently so their register association is clear.

This improves code maintainability and eases future reference to the
controller manual.

No functional change intended.

Co-developed-by: Feizhou Yu <yufeizhou201@163.com>
Signed-off-by: Feizhou Yu <yufeizhou201@163.com>
Signed-off-by: Hans Zhang <18255117159@163.com>
---
 drivers/pci/controller/dwc/pci-imx6.c         |  26 +-
 drivers/pci/controller/dwc/pci-keystone.c     |   4 +-
 .../pci/controller/dwc/pcie-designware-ep.c   |  10 +-
 .../pci/controller/dwc/pcie-designware-host.c |  18 +-
 drivers/pci/controller/dwc/pcie-designware.c  | 176 ++++++------
 drivers/pci/controller/dwc/pcie-designware.h  | 263 +++++++++---------
 drivers/pci/controller/dwc/pcie-fu740.c       |   6 +-
 drivers/pci/controller/dwc/pcie-nxp-s32g.c    |  18 +-
 drivers/pci/controller/dwc/pcie-qcom-common.c |  28 +-
 drivers/pci/controller/dwc/pcie-qcom.c        |   6 +-
 drivers/pci/controller/dwc/pcie-rcar-gen4.c   |  26 +-
 .../pci/controller/dwc/pcie-tegra194-acpi.c   |  22 +-
 drivers/pci/controller/dwc/pcie-tegra194.c    |  86 +++---
 drivers/pci/controller/dwc/pcie-ultrarisc.c   |  10 +-
 14 files changed, 349 insertions(+), 350 deletions(-)

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 39790e66b98d..8383a71534c0 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -955,9 +955,9 @@ static int imx_pcie_wait_for_speed_change(struct imx_pcie *imx_pcie)
 	unsigned int retries;
 
 	for (retries = 0; retries < 200; retries++) {
-		tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
+		tmp = dw_pcie_readl_dbi(pci, LINK_WIDTH_SPEED_CTRL);
 		/* Test if the speed change finished. */
-		if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
+		if (!(tmp & SPEED_CHANGE))
 			return 0;
 		usleep_range(100, 1000);
 	}
@@ -1040,9 +1040,9 @@ static int imx_pcie_start_link(struct dw_pcie *pci)
 		 * Start Directed Speed Change so the best possible
 		 * speed both link partners support can be negotiated.
 		 */
-		tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
-		tmp |= PORT_LOGIC_SPEED_CHANGE;
-		dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
+		tmp = dw_pcie_readl_dbi(pci, LINK_WIDTH_SPEED_CTRL);
+		tmp |= SPEED_CHANGE;
+		dw_pcie_writel_dbi(pci, LINK_WIDTH_SPEED_CTRL, tmp);
 		dw_pcie_dbi_ro_wr_dis(pci);
 
 		ret = imx_pcie_wait_for_speed_change(imx_pcie);
@@ -1058,8 +1058,8 @@ static int imx_pcie_start_link(struct dw_pcie *pci)
 
 err_reset_phy:
 	dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",
-		dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0),
-		dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1));
+		dw_pcie_readl_dbi(pci, PORT_LINK_DEBUG0),
+		dw_pcie_readl_dbi(pci, PORT_LINK_DEBUG1));
 	imx_pcie_reset_phy(imx_pcie);
 	return 0;
 }
@@ -1498,18 +1498,18 @@ static void imx_pcie_host_post_init(struct dw_pcie_rp *pp)
 		/*
 		 * ERR051586: Compliance with 8GT/s Receiver Impedance ECN
 		 *
-		 * The default value of GEN3_RELATED_OFF[GEN3_ZRXDC_NONCOMPL]
+		 * The default value of GEN3_CTRL[GEN3_ZRXDC_NONCOMPL]
 		 * is 1 which makes receiver non-compliant with the ZRX-DC
 		 * parameter for 2.5 GT/s when operating at 8 GT/s or higher.
 		 * It causes unnecessary timeout in L1.
 		 *
-		 * Workaround: Program GEN3_RELATED_OFF[GEN3_ZRXDC_NONCOMPL]
+		 * Workaround: Program GEN3_CTRL[GEN3_ZRXDC_NONCOMPL]
 		 * to 0.
 		 */
 		dw_pcie_dbi_ro_wr_en(pci);
-		val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
-		val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL;
-		dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
+		val = dw_pcie_readl_dbi(pci, GEN3_CTRL);
+		val &= ~GEN3_CTRL_GEN3_ZRXDC_NONCOMPL;
+		dw_pcie_writel_dbi(pci, GEN3_CTRL, val);
 		dw_pcie_dbi_ro_wr_dis(pci);
 	}
 
@@ -1521,7 +1521,7 @@ static void imx_pcie_host_post_init(struct dw_pcie_rp *pp)
 }
 
 /*
- * In old DWC implementations, PCIE_ATU_INHIBIT_PAYLOAD in iATU Ctrl2
+ * In old DWC implementations, ATU_INHIBIT_PAYLOAD in iATU Ctrl2
  * register is reserved, so the generic DWC implementation of sending the
  * PME_Turn_Off message using a dummy MMIO write cannot be used.
  */
diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c
index 602516239a57..c0806744544e 100644
--- a/drivers/pci/controller/dwc/pci-keystone.c
+++ b/drivers/pci/controller/dwc/pci-keystone.c
@@ -497,8 +497,8 @@ static bool ks_pcie_link_up(struct dw_pcie *pci)
 {
 	u32 val;
 
-	val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0);
-	return (val & PORT_LOGIC_LTSSM_STATE_MASK) == PORT_LOGIC_LTSSM_STATE_L0;
+	val = dw_pcie_readl_dbi(pci, PORT_LINK_DEBUG0);
+	return (val & PORT_LINK_DEBUG0_LTSSM_MASK) == DW_PCIE_LTSSM_L0;
 }
 
 static void ks_pcie_stop_link(struct dw_pcie *pci)
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index de8ee3db4360..0262d85ed390 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -163,7 +163,7 @@ static void dw_pcie_ep_clear_ib_maps(struct dw_pcie_ep *ep, u8 func_no, enum pci
 	/* Tear down the BAR Match Mode mapping, if any. */
 	if (ep_func->bar_to_atu[bar]) {
 		atu_index = ep_func->bar_to_atu[bar] - 1;
-		dw_pcie_disable_atu(pci, PCIE_ATU_REGION_DIR_IB, atu_index);
+		dw_pcie_disable_atu(pci, ATU_REGION_DIR_IB, atu_index);
 		clear_bit(atu_index, ep->ib_window_map);
 		ep_func->bar_to_atu[bar] = 0;
 		return;
@@ -177,7 +177,7 @@ static void dw_pcie_ep_clear_ib_maps(struct dw_pcie_ep *ep, u8 func_no, enum pci
 	if (!indexes)
 		return;
 	for (i = 0; i < num; i++) {
-		dw_pcie_disable_atu(pci, PCIE_ATU_REGION_DIR_IB, indexes[i]);
+		dw_pcie_disable_atu(pci, ATU_REGION_DIR_IB, indexes[i]);
 		clear_bit(indexes[i], ep->ib_window_map);
 	}
 	devm_kfree(dev, indexes);
@@ -647,7 +647,7 @@ static void dw_pcie_ep_unmap_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
 		return;
 
 	ep->outbound_addr[atu_index] = 0;
-	dw_pcie_disable_atu(pci, PCIE_ATU_REGION_DIR_OB, atu_index);
+	dw_pcie_disable_atu(pci, ATU_REGION_DIR_OB, atu_index);
 	clear_bit(atu_index, ep->ob_window_map);
 }
 
@@ -1077,10 +1077,10 @@ int dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep *ep, u8 func_no,
 	if (!ep_func || !ep_func->msix_cap)
 		return -EINVAL;
 
-	msg_data = (func_no << PCIE_MSIX_DOORBELL_PF_SHIFT) |
+	msg_data = (func_no << MSIX_DOORBELL_PF_SHIFT) |
 		   (interrupt_num - 1);
 
-	dw_pcie_writel_dbi(pci, PCIE_MSIX_DOORBELL, msg_data);
+	dw_pcie_writel_dbi(pci, MSIX_DOORBELL, msg_data);
 
 	return 0;
 }
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index f5a38e6fd8d7..77aa79ef0ccf 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -440,7 +440,7 @@ static int dw_pcie_config_ecam_iatu(struct dw_pcie_rp *pp)
 	atu.parent_bus_addr = pp->cfg0_base + SZ_1M;
 	/* 1MiB is to cover 1 (bus) * 32 (devices) * 8 (functions) */
 	atu.size = SZ_1M;
-	atu.ctrl2 = PCIE_ATU_CFG_SHIFT_MODE_ENABLE;
+	atu.ctrl2 = ATU_CFG_SHIFT_MODE_ENABLE;
 	ret = dw_pcie_prog_outbound_atu(pci, &atu);
 	if (ret)
 		return ret;
@@ -455,7 +455,7 @@ static int dw_pcie_config_ecam_iatu(struct dw_pcie_rp *pp)
 	atu.type = PCIE_TLP_TYPE_CFG1_RDWR;
 	atu.parent_bus_addr = pp->cfg0_base + SZ_2M;
 	atu.size = (SZ_1M * bus_range_max) - SZ_2M;
-	atu.ctrl2 = PCIE_ATU_CFG_SHIFT_MODE_ENABLE;
+	atu.ctrl2 = ATU_CFG_SHIFT_MODE_ENABLE;
 
 	return dw_pcie_prog_outbound_atu(pci, &atu);
 }
@@ -747,8 +747,8 @@ static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus,
 	if (!dw_pcie_link_up(pci))
 		return NULL;
 
-	busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
-		 PCIE_ATU_FUNC(PCI_FUNC(devfn));
+	busdev = ATU_BUS(bus->number) | ATU_DEV(PCI_SLOT(devfn)) |
+		 ATU_FUNC(PCI_FUNC(devfn));
 
 	if (pci_is_root_bus(bus->parent))
 		type = PCIE_TLP_TYPE_CFG0_RDWR;
@@ -884,10 +884,10 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
 	 * the MEM/IO (dma-)ranges setups.
 	 */
 	for (i = 0; i < pci->num_ob_windows; i++)
-		dw_pcie_disable_atu(pci, PCIE_ATU_REGION_DIR_OB, i);
+		dw_pcie_disable_atu(pci, ATU_REGION_DIR_OB, i);
 
 	for (i = 0; i < pci->num_ib_windows; i++)
-		dw_pcie_disable_atu(pci, PCIE_ATU_REGION_DIR_IB, i);
+		dw_pcie_disable_atu(pci, ATU_REGION_DIR_IB, i);
 
 	/*
 	 * NOTE: For outbound address translation, outbound iATU at index 0 is
@@ -1165,9 +1165,9 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp)
 	/* Program correct class for RC */
 	dw_pcie_writew_dbi(pci, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI);
 
-	val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
-	val |= PORT_LOGIC_SPEED_CHANGE;
-	dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
+	val = dw_pcie_readl_dbi(pci, LINK_WIDTH_SPEED_CTRL);
+	val |= SPEED_CHANGE;
+	dw_pcie_writel_dbi(pci, LINK_WIDTH_SPEED_CTRL, val);
 
 	dw_pcie_dbi_ro_wr_dis(pci);
 
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 593388f29bdd..855d2a54b3c6 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -436,9 +436,9 @@ static inline void __iomem *dw_pcie_select_atu(struct dw_pcie *pci, u32 dir,
 					       u32 index)
 {
 	if (dw_pcie_cap_is(pci, IATU_UNROLL))
-		return pci->atu_base + PCIE_ATU_UNROLL_BASE(dir, index);
+		return pci->atu_base + ATU_UNROLL_BASE(dir, index);
 
-	dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, dir | index);
+	dw_pcie_writel_dbi(pci, IATU_VIEWPORT, dir | index);
 	return pci->atu_base;
 }
 
@@ -480,13 +480,13 @@ static void dw_pcie_writel_atu(struct dw_pcie *pci, u32 dir, u32 index,
 
 static inline u32 dw_pcie_readl_atu_ob(struct dw_pcie *pci, u32 index, u32 reg)
 {
-	return dw_pcie_readl_atu(pci, PCIE_ATU_REGION_DIR_OB, index, reg);
+	return dw_pcie_readl_atu(pci, ATU_REGION_DIR_OB, index, reg);
 }
 
 static inline void dw_pcie_writel_atu_ob(struct dw_pcie *pci, u32 index, u32 reg,
 					 u32 val)
 {
-	dw_pcie_writel_atu(pci, PCIE_ATU_REGION_DIR_OB, index, reg, val);
+	dw_pcie_writel_atu(pci, ATU_REGION_DIR_OB, index, reg, val);
 }
 
 static inline u32 dw_pcie_enable_ecrc(u32 val)
@@ -527,7 +527,7 @@ static inline u32 dw_pcie_enable_ecrc(u32 val)
 	 * handle the scenario is to program TD bit by default.
 	 */
 
-	return val | PCIE_ATU_TD;
+	return val | ATU_TD;
 }
 
 int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
@@ -548,44 +548,44 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
 		return -EINVAL;
 	}
 
-	dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_BASE,
+	dw_pcie_writel_atu_ob(pci, atu->index, ATU_LOWER_BASE,
 			      lower_32_bits(parent_bus_addr));
-	dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_BASE,
+	dw_pcie_writel_atu_ob(pci, atu->index, ATU_UPPER_BASE,
 			      upper_32_bits(parent_bus_addr));
 
-	dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LIMIT,
+	dw_pcie_writel_atu_ob(pci, atu->index, ATU_LIMIT,
 			      lower_32_bits(limit_addr));
 	if (dw_pcie_ver_is_ge(pci, 460A))
-		dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_LIMIT,
+		dw_pcie_writel_atu_ob(pci, atu->index, ATU_UPPER_LIMIT,
 				      upper_32_bits(limit_addr));
 
-	dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_TARGET,
+	dw_pcie_writel_atu_ob(pci, atu->index, ATU_LOWER_TARGET,
 			      lower_32_bits(atu->pci_addr));
-	dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_TARGET,
+	dw_pcie_writel_atu_ob(pci, atu->index, ATU_UPPER_TARGET,
 			      upper_32_bits(atu->pci_addr));
 
-	val = atu->type | atu->routing | PCIE_ATU_FUNC_NUM(atu->func_no);
+	val = atu->type | atu->routing | ATU_FUNC_NUM(atu->func_no);
 	if (upper_32_bits(limit_addr) > upper_32_bits(parent_bus_addr) &&
 	    dw_pcie_ver_is_ge(pci, 460A))
-		val |= PCIE_ATU_INCREASE_REGION_SIZE;
+		val |= ATU_INCREASE_REGION_SIZE;
 	if (!dw_pcie_ver_is_ge(pci, 510A))
 		val = dw_pcie_enable_ecrc(val);
-	dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val);
+	dw_pcie_writel_atu_ob(pci, atu->index, ATU_REGION_CTRL1, val);
 
-	val = PCIE_ATU_ENABLE | atu->ctrl2;
+	val = ATU_ENABLE | atu->ctrl2;
 	if (atu->type == PCIE_TLP_TYPE_MSG) {
 		/* The data-less messages only for now */
-		val |= PCIE_ATU_INHIBIT_PAYLOAD | atu->code;
+		val |= ATU_INHIBIT_PAYLOAD | atu->code;
 	}
-	dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, val);
+	dw_pcie_writel_atu_ob(pci, atu->index, ATU_REGION_CTRL2, val);
 
 	/*
 	 * Make sure ATU enable takes effect before any subsequent config
 	 * and I/O accesses.
 	 */
 	for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
-		val = dw_pcie_readl_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2);
-		if (val & PCIE_ATU_ENABLE)
+		val = dw_pcie_readl_atu_ob(pci, atu->index, ATU_REGION_CTRL2);
+		if (val & ATU_ENABLE)
 			return 0;
 
 		mdelay(LINK_WAIT_IATU);
@@ -598,13 +598,13 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
 
 static inline u32 dw_pcie_readl_atu_ib(struct dw_pcie *pci, u32 index, u32 reg)
 {
-	return dw_pcie_readl_atu(pci, PCIE_ATU_REGION_DIR_IB, index, reg);
+	return dw_pcie_readl_atu(pci, ATU_REGION_DIR_IB, index, reg);
 }
 
 static inline void dw_pcie_writel_atu_ib(struct dw_pcie *pci, u32 index, u32 reg,
 					 u32 val)
 {
-	dw_pcie_writel_atu(pci, PCIE_ATU_REGION_DIR_IB, index, reg, val);
+	dw_pcie_writel_atu(pci, ATU_REGION_DIR_IB, index, reg, val);
 }
 
 int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type,
@@ -622,36 +622,36 @@ int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type,
 		return -EINVAL;
 	}
 
-	dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LOWER_BASE,
+	dw_pcie_writel_atu_ib(pci, index, ATU_LOWER_BASE,
 			      lower_32_bits(pci_addr));
-	dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_BASE,
+	dw_pcie_writel_atu_ib(pci, index, ATU_UPPER_BASE,
 			      upper_32_bits(pci_addr));
 
-	dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LIMIT,
+	dw_pcie_writel_atu_ib(pci, index, ATU_LIMIT,
 			      lower_32_bits(limit_addr));
 	if (dw_pcie_ver_is_ge(pci, 460A))
-		dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_LIMIT,
+		dw_pcie_writel_atu_ib(pci, index, ATU_UPPER_LIMIT,
 				      upper_32_bits(limit_addr));
 
-	dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LOWER_TARGET,
+	dw_pcie_writel_atu_ib(pci, index, ATU_LOWER_TARGET,
 			      lower_32_bits(parent_bus_addr));
-	dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_TARGET,
+	dw_pcie_writel_atu_ib(pci, index, ATU_UPPER_TARGET,
 			      upper_32_bits(parent_bus_addr));
 
 	val = type;
 	if (upper_32_bits(limit_addr) > upper_32_bits(pci_addr) &&
 	    dw_pcie_ver_is_ge(pci, 460A))
-		val |= PCIE_ATU_INCREASE_REGION_SIZE;
-	dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL1, val);
-	dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE);
+		val |= ATU_INCREASE_REGION_SIZE;
+	dw_pcie_writel_atu_ib(pci, index, ATU_REGION_CTRL1, val);
+	dw_pcie_writel_atu_ib(pci, index, ATU_REGION_CTRL2, ATU_ENABLE);
 
 	/*
 	 * Make sure ATU enable takes effect before any subsequent config
 	 * and I/O accesses.
 	 */
 	for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
-		val = dw_pcie_readl_atu_ib(pci, index, PCIE_ATU_REGION_CTRL2);
-		if (val & PCIE_ATU_ENABLE)
+		val = dw_pcie_readl_atu_ib(pci, index, ATU_REGION_CTRL2);
+		if (val & ATU_ENABLE)
 			return 0;
 
 		mdelay(LINK_WAIT_IATU);
@@ -671,24 +671,24 @@ int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index,
 	    !IS_ALIGNED(parent_bus_addr, size))
 		return -EINVAL;
 
-	dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LOWER_TARGET,
+	dw_pcie_writel_atu_ib(pci, index, ATU_LOWER_TARGET,
 			      lower_32_bits(parent_bus_addr));
-	dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_TARGET,
+	dw_pcie_writel_atu_ib(pci, index, ATU_UPPER_TARGET,
 			      upper_32_bits(parent_bus_addr));
 
-	dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL1, type |
-			      PCIE_ATU_FUNC_NUM(func_no));
-	dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL2,
-			      PCIE_ATU_ENABLE | PCIE_ATU_FUNC_NUM_MATCH_EN |
-			      PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
+	dw_pcie_writel_atu_ib(pci, index, ATU_REGION_CTRL1, type |
+			      ATU_FUNC_NUM(func_no));
+	dw_pcie_writel_atu_ib(pci, index, ATU_REGION_CTRL2,
+			      ATU_ENABLE | ATU_FUNC_NUM_MATCH_EN |
+			      ATU_BAR_MODE_ENABLE | (bar << 8));
 
 	/*
 	 * Make sure ATU enable takes effect before any subsequent config
 	 * and I/O accesses.
 	 */
 	for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
-		val = dw_pcie_readl_atu_ib(pci, index, PCIE_ATU_REGION_CTRL2);
-		if (val & PCIE_ATU_ENABLE)
+		val = dw_pcie_readl_atu_ib(pci, index, ATU_REGION_CTRL2);
+		if (val & ATU_ENABLE)
 			return 0;
 
 		mdelay(LINK_WAIT_IATU);
@@ -701,7 +701,7 @@ int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index,
 
 void dw_pcie_disable_atu(struct dw_pcie *pci, u32 dir, int index)
 {
-	dw_pcie_writel_atu(pci, dir, index, PCIE_ATU_REGION_CTRL2, 0);
+	dw_pcie_writel_atu(pci, dir, index, ATU_REGION_CTRL2, 0);
 }
 
 const char *dw_pcie_ltssm_status_string(enum dw_pcie_ltssm ltssm)
@@ -824,9 +824,9 @@ bool dw_pcie_link_up(struct dw_pcie *pci)
 	if (pci->ops && pci->ops->link_up)
 		return pci->ops->link_up(pci);
 
-	val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1);
-	return ((val & PCIE_PORT_DEBUG1_LINK_UP) &&
-		(!(val & PCIE_PORT_DEBUG1_LINK_IN_TRAINING)));
+	val = dw_pcie_readl_dbi(pci, PORT_LINK_DEBUG1);
+	return ((val & PORT_LINK_DEBUG1_LINK_UP) &&
+		(!(val & PORT_LINK_DEBUG1_LINK_IN_TRAINING)));
 }
 EXPORT_SYMBOL_GPL(dw_pcie_link_up);
 
@@ -834,9 +834,9 @@ void dw_pcie_upconfig_setup(struct dw_pcie *pci)
 {
 	u32 val;
 
-	val = dw_pcie_readl_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL);
-	val |= PORT_MLTI_UPCFG_SUPPORT;
-	dw_pcie_writel_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL, val);
+	val = dw_pcie_readl_dbi(pci, MULTI_LANE_CTRL);
+	val |= MULTI_LANE_CTRL_UPCFG_SUPPORT;
+	dw_pcie_writel_dbi(pci, MULTI_LANE_CTRL, val);
 }
 EXPORT_SYMBOL_GPL(dw_pcie_upconfig_setup);
 
@@ -894,36 +894,36 @@ static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)
 		return;
 
 	/* Set the number of lanes */
-	plc = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
-	plc &= ~PORT_LINK_FAST_LINK_MODE;
-	plc &= ~PORT_LINK_MODE_MASK;
+	plc = dw_pcie_readl_dbi(pci, PORT_LINK_CTRL);
+	plc &= ~PORT_LINK_CTRL_FLM;
+	plc &= ~PORT_LINK_CTRL_LC_MASK;
 
 	/* Set link width speed control register */
-	lwsc = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
-	lwsc &= ~PORT_LOGIC_LINK_WIDTH_MASK;
-	lwsc |= PORT_LOGIC_LINK_WIDTH_1_LANES;
+	lwsc = dw_pcie_readl_dbi(pci, LINK_WIDTH_SPEED_CTRL);
+	lwsc &= ~LINK_WIDTH_MASK;
+	lwsc |= LINK_WIDTH_1_LANES;
 	switch (num_lanes) {
 	case 1:
-		plc |= PORT_LINK_MODE_1_LANES;
+		plc |= PORT_LINK_CTRL_LC_1_LANES;
 		break;
 	case 2:
-		plc |= PORT_LINK_MODE_2_LANES;
+		plc |= PORT_LINK_CTRL_LC_2_LANES;
 		break;
 	case 4:
-		plc |= PORT_LINK_MODE_4_LANES;
+		plc |= PORT_LINK_CTRL_LC_4_LANES;
 		break;
 	case 8:
-		plc |= PORT_LINK_MODE_8_LANES;
+		plc |= PORT_LINK_CTRL_LC_8_LANES;
 		break;
 	case 16:
-		plc |= PORT_LINK_MODE_16_LANES;
+		plc |= PORT_LINK_CTRL_LC_16_LANES;
 		break;
 	default:
 		dev_err(pci->dev, "num-lanes %u: invalid value\n", num_lanes);
 		return;
 	}
-	dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, plc);
-	dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, lwsc);
+	dw_pcie_writel_dbi(pci, PORT_LINK_CTRL, plc);
+	dw_pcie_writel_dbi(pci, LINK_WIDTH_SPEED_CTRL, lwsc);
 
 	cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
 	lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP);
@@ -937,48 +937,48 @@ void dw_pcie_iatu_detect(struct dw_pcie *pci)
 	u32 val, min, dir;
 	u64 max;
 
-	val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT);
+	val = dw_pcie_readl_dbi(pci, IATU_VIEWPORT);
 	if (val == 0xFFFFFFFF) {
 		dw_pcie_cap_set(pci, IATU_UNROLL);
 
 		max_region = min((int)pci->atu_size / 512, 256);
 	} else {
-		pci->atu_base = pci->dbi_base + PCIE_ATU_VIEWPORT_BASE;
-		pci->atu_size = PCIE_ATU_VIEWPORT_SIZE;
+		pci->atu_base = pci->dbi_base + ATU_VIEWPORT_BASE;
+		pci->atu_size = ATU_VIEWPORT_SIZE;
 
-		dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, 0xFF);
-		max_region = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT) + 1;
+		dw_pcie_writel_dbi(pci, IATU_VIEWPORT, 0xFF);
+		max_region = dw_pcie_readl_dbi(pci, IATU_VIEWPORT) + 1;
 	}
 
 	for (ob = 0; ob < max_region; ob++) {
-		dw_pcie_writel_atu_ob(pci, ob, PCIE_ATU_LOWER_TARGET, 0x11110000);
-		val = dw_pcie_readl_atu_ob(pci, ob, PCIE_ATU_LOWER_TARGET);
+		dw_pcie_writel_atu_ob(pci, ob, ATU_LOWER_TARGET, 0x11110000);
+		val = dw_pcie_readl_atu_ob(pci, ob, ATU_LOWER_TARGET);
 		if (val != 0x11110000)
 			break;
 	}
 
 	for (ib = 0; ib < max_region; ib++) {
-		dw_pcie_writel_atu_ib(pci, ib, PCIE_ATU_LOWER_TARGET, 0x11110000);
-		val = dw_pcie_readl_atu_ib(pci, ib, PCIE_ATU_LOWER_TARGET);
+		dw_pcie_writel_atu_ib(pci, ib, ATU_LOWER_TARGET, 0x11110000);
+		val = dw_pcie_readl_atu_ib(pci, ib, ATU_LOWER_TARGET);
 		if (val != 0x11110000)
 			break;
 	}
 
 	if (ob) {
-		dir = PCIE_ATU_REGION_DIR_OB;
+		dir = ATU_REGION_DIR_OB;
 	} else if (ib) {
-		dir = PCIE_ATU_REGION_DIR_IB;
+		dir = ATU_REGION_DIR_IB;
 	} else {
 		dev_err(pci->dev, "No iATU regions found\n");
 		return;
 	}
 
-	dw_pcie_writel_atu(pci, dir, 0, PCIE_ATU_LIMIT, 0x0);
-	min = dw_pcie_readl_atu(pci, dir, 0, PCIE_ATU_LIMIT);
+	dw_pcie_writel_atu(pci, dir, 0, ATU_LIMIT, 0x0);
+	min = dw_pcie_readl_atu(pci, dir, 0, ATU_LIMIT);
 
 	if (dw_pcie_ver_is_ge(pci, 460A)) {
-		dw_pcie_writel_atu(pci, dir, 0, PCIE_ATU_UPPER_LIMIT, 0xFFFFFFFF);
-		max = dw_pcie_readl_atu(pci, dir, 0, PCIE_ATU_UPPER_LIMIT);
+		dw_pcie_writel_atu(pci, dir, 0, ATU_UPPER_LIMIT, 0xFFFFFFFF);
+		max = dw_pcie_readl_atu(pci, dir, 0, ATU_UPPER_LIMIT);
 	} else {
 		max = 0;
 	}
@@ -1273,19 +1273,19 @@ void dw_pcie_setup(struct dw_pcie *pci)
 
 	/* Configure Gen1 N_FTS */
 	if (pci->n_fts[0]) {
-		val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR);
-		val &= ~(PORT_AFR_N_FTS_MASK | PORT_AFR_CC_N_FTS_MASK);
-		val |= PORT_AFR_N_FTS(pci->n_fts[0]);
-		val |= PORT_AFR_CC_N_FTS(pci->n_fts[0]);
-		dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val);
+		val = dw_pcie_readl_dbi(pci, PORT_AFAC);
+		val &= ~(PORT_AFAC_N_FTS_MASK | PORT_AFAC_CC_N_FTS_MASK);
+		val |= PORT_AFAC_N_FTS(pci->n_fts[0]);
+		val |= PORT_AFAC_CC_N_FTS(pci->n_fts[0]);
+		dw_pcie_writel_dbi(pci, PORT_AFAC, val);
 	}
 
 	/* Configure Gen2+ N_FTS */
 	if (pci->n_fts[1]) {
-		val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
-		val &= ~PORT_LOGIC_N_FTS_MASK;
+		val = dw_pcie_readl_dbi(pci, LINK_WIDTH_SPEED_CTRL);
+		val &= ~N_FTS_MASK;
 		val |= pci->n_fts[1];
-		dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
+		dw_pcie_writel_dbi(pci, LINK_WIDTH_SPEED_CTRL, val);
 	}
 
 	if (dw_pcie_cap_is(pci, CDM_CHECK)) {
@@ -1295,10 +1295,10 @@ void dw_pcie_setup(struct dw_pcie *pci)
 		dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val);
 	}
 
-	val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
-	val &= ~PORT_LINK_FAST_LINK_MODE;
-	val |= PORT_LINK_DLL_LINK_EN;
-	dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
+	val = dw_pcie_readl_dbi(pci, PORT_LINK_CTRL);
+	val &= ~PORT_LINK_CTRL_FLM;
+	val |= PORT_LINK_CTRL_DLE;
+	dw_pcie_writel_dbi(pci, PORT_LINK_CTRL, val);
 
 	dw_pcie_link_set_max_link_width(pci, pci->num_lanes);
 }
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 0735ae940924..10bf06427e41 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -71,38 +71,38 @@
 #define LINK_WAIT_IATU			9
 
 /* Synopsys-specific PCIe configuration registers */
-#define PCIE_PORT_FORCE			0x708
+#define PORT_FORCE_LINK			0x708		/* Port Force Link */
 /* Bit[7:0] LINK_NUM: Link Number. Not used for endpoint */
-#define PORT_LINK_NUM_MASK		GENMASK(7, 0)
-#define PORT_FORCE_DO_DESKEW_FOR_SRIS	BIT(23)
-
-#define PCIE_PORT_AFR			0x70C
-#define PORT_AFR_N_FTS_MASK		GENMASK(15, 8)
-#define PORT_AFR_N_FTS(n)		FIELD_PREP(PORT_AFR_N_FTS_MASK, n)
-#define PORT_AFR_CC_N_FTS_MASK		GENMASK(23, 16)
-#define PORT_AFR_CC_N_FTS(n)		FIELD_PREP(PORT_AFR_CC_N_FTS_MASK, n)
-#define PORT_AFR_ENTER_ASPM		BIT(30)
-#define PORT_AFR_L0S_ENTRANCE_LAT_SHIFT	24
-#define PORT_AFR_L0S_ENTRANCE_LAT_MASK	GENMASK(26, 24)
-#define PORT_AFR_L1_ENTRANCE_LAT_SHIFT	27
-#define PORT_AFR_L1_ENTRANCE_LAT_MASK	GENMASK(29, 27)
-
-#define PCIE_PORT_LINK_CONTROL		0x710
-#define PORT_LINK_DLL_LINK_EN		BIT(5)
-#define PORT_LINK_FAST_LINK_MODE	BIT(7)
-#define PORT_LINK_MODE_MASK		GENMASK(21, 16)
-#define PORT_LINK_MODE(n)		FIELD_PREP(PORT_LINK_MODE_MASK, n)
-#define PORT_LINK_MODE_1_LANES		PORT_LINK_MODE(0x1)
-#define PORT_LINK_MODE_2_LANES		PORT_LINK_MODE(0x3)
-#define PORT_LINK_MODE_4_LANES		PORT_LINK_MODE(0x7)
-#define PORT_LINK_MODE_8_LANES		PORT_LINK_MODE(0xf)
-#define PORT_LINK_MODE_16_LANES		PORT_LINK_MODE(0x1f)
-
-#define PCIE_PORT_LANE_SKEW		0x714
-#define PORT_LANE_SKEW_INSERT_MASK	GENMASK(23, 0)
+#define  PORT_FORCE_LINK_NUM_MASK	GENMASK(7, 0)	/* Link Number. Not used for endpoint */
+#define  PORT_FORCE_LINK_DDFS		BIT(23)		/* do deskew for sris */
+
+#define PORT_AFAC			0x70C		/* Ack Frequency and L0-L1 ASPM Control */
+#define  PORT_AFAC_N_FTS_MASK		GENMASK(15, 8)	/* Ack the number of Fast Training Sequence mask */
+#define  PORT_AFAC_N_FTS(n)		FIELD_PREP(PORT_AFAC_N_FTS_MASK, n)	/* Ack the number of Fast Training Sequence */
+#define  PORT_AFAC_CC_N_FTS_MASK	GENMASK(23, 16)	/* Common Clock N_FTS mask */
+#define  PORT_AFAC_CC_N_FTS(n)		FIELD_PREP(PORT_AFAC_CC_N_FTS_MASK, n)	/* Common Clock N_FTS */
+#define  PORT_AFAC_ENTER_ASPM		BIT(30)		/* ASPM L1 Entry Control */
+#define  PORT_AFAC_L0S_ELS		24		/* L0s Entrance Latency shift */
+#define  PORT_AFAC_L0S_ELM		GENMASK(26, 24)	/* L0s Entrance Latency mask */
+#define  PORT_AFAC_L1_ELS		27		/* L1 Entrance Latency shift */
+#define  PORT_AFAC_L1_ELM		GENMASK(29, 27)	/* L1 Entrance Latency mask */
+
+#define PORT_LINK_CTRL			0x710		/* Port Link Control Register */
+#define  PORT_LINK_CTRL_DLE		BIT(5)		/* DLL Link Enable */
+#define  PORT_LINK_CTRL_FLM		BIT(7)		/* Fast Link Mode */
+#define  PORT_LINK_CTRL_LC_MASK		GENMASK(21, 16)	/* Link Mode Enable (LINK_CAPABLE) mask */
+#define  PORT_LINK_CTRL_LC(n)		FIELD_PREP(PORT_LINK_CTRL_LC_MASK, n)	/* Link Mode Enable (LINK_CAPABLE) */
+#define  PORT_LINK_CTRL_LC_1_LANES	PORT_LINK_CTRL_LC(0x1)	/* Link Mode 1 lane */
+#define  PORT_LINK_CTRL_LC_2_LANES	PORT_LINK_CTRL_LC(0x3)	/* Link Mode 2 lane */
+#define  PORT_LINK_CTRL_LC_4_LANES	PORT_LINK_CTRL_LC(0x7)	/* Link Mode 4 lane */
+#define  PORT_LINK_CTRL_LC_8_LANES	PORT_LINK_CTRL_LC(0xf)	/* Link Mode 8 lane */
+#define  PORT_LINK_CTRL_LC_16_LANES	PORT_LINK_CTRL_LC(0x1f)	/* Link Mode 16 lane */
+
+#define PORT_LANE_SKEW			0x714		/* Lane Skew */
+#define  PORT_LANE_SKEW_INSERT_MASK	GENMASK(23, 0)
 
 /*
- * PCIE_TIMER_CTRL_MAX_FUNC_NUM: Timer Control and Max Function Number
+ * TIMER_CTRL_MAX_FUNC_NUM: Timer Control and Max Function Number
  * Register.
  *
  * This register holds the ack frequency, latency, replay, fast link
@@ -116,68 +116,70 @@
  *   0x2 (SF_64): Scaling Factor is 64 (1ms is 16us)
  *   0x3 (SF_16): Scaling Factor is 16 (1ms is 64us)
  */
-#define PCIE_TIMER_CTRL_MAX_FUNC_NUM	0x718
-#define PORT_FLT_SF_MASK	GENMASK(30, 29)
-#define PORT_FLT_SF_VAL_1024	0x0
-#define PORT_FLT_SF_VAL_256	0x1
-#define PORT_FLT_SF_VAL_64	0x2
-#define PORT_FLT_SF_VAL_16	0x3
-
-#define PCIE_PORT_DEBUG0		0x728
-#define PORT_LOGIC_LTSSM_STATE_MASK	0x3f
-#define PORT_LOGIC_LTSSM_STATE_L0	0x11
-#define PCIE_PORT_DEBUG1		0x72C
-#define PCIE_PORT_DEBUG1_LINK_UP		BIT(4)
-#define PCIE_PORT_DEBUG1_LINK_IN_TRAINING	BIT(29)
-
-#define PCIE_LINK_WIDTH_SPEED_CONTROL	0x80C
-#define PORT_LOGIC_N_FTS_MASK		GENMASK(7, 0)
-#define PORT_LOGIC_SPEED_CHANGE		BIT(17)
-#define PORT_LOGIC_LINK_WIDTH_MASK	GENMASK(12, 8)
-#define PORT_LOGIC_LINK_WIDTH(n)	FIELD_PREP(PORT_LOGIC_LINK_WIDTH_MASK, n)
-#define PORT_LOGIC_LINK_WIDTH_1_LANES	PORT_LOGIC_LINK_WIDTH(0x1)
-#define PORT_LOGIC_LINK_WIDTH_2_LANES	PORT_LOGIC_LINK_WIDTH(0x2)
-#define PORT_LOGIC_LINK_WIDTH_4_LANES	PORT_LOGIC_LINK_WIDTH(0x4)
-#define PORT_LOGIC_LINK_WIDTH_8_LANES	PORT_LOGIC_LINK_WIDTH(0x8)
-
-#define PCIE_MSI_ADDR_LO		0x820
-#define PCIE_MSI_ADDR_HI		0x824
-#define PCIE_MSI_INTR0_ENABLE		0x828
-#define PCIE_MSI_INTR0_MASK		0x82C
-#define PCIE_MSI_INTR0_STATUS		0x830
-
-#define GEN3_RELATED_OFF			0x890
-#define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL	BIT(0)
-#define GEN3_RELATED_OFF_EQ_PHASE_2_3		BIT(9)
-#define GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS	BIT(13)
-#define GEN3_RELATED_OFF_GEN3_EQ_DISABLE	BIT(16)
-#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT	24
-#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK	GENMASK(25, 24)
-
-#define GEN3_EQ_CONTROL_OFF			0x8A8
-#define GEN3_EQ_CONTROL_OFF_FB_MODE		GENMASK(3, 0)
-#define GEN3_EQ_CONTROL_OFF_PHASE23_EXIT_MODE	BIT(4)
-#define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC	GENMASK(23, 8)
-#define GEN3_EQ_CONTROL_OFF_FOM_INC_INITIAL_EVAL	BIT(24)
-
-#define GEN3_EQ_FB_MODE_DIR_CHANGE_OFF		0x8AC
-#define GEN3_EQ_FMDC_T_MIN_PHASE23		GENMASK(4, 0)
-#define GEN3_EQ_FMDC_N_EVALS			GENMASK(9, 5)
-#define GEN3_EQ_FMDC_MAX_PRE_CURSOR_DELTA	GENMASK(13, 10)
-#define GEN3_EQ_FMDC_MAX_POST_CURSOR_DELTA	GENMASK(17, 14)
-
-#define COHERENCY_CONTROL_1_OFF			0x8E0
-#define CFG_MEMTYPE_BOUNDARY_LOW_ADDR_MASK	GENMASK(31, 2)
-#define CFG_MEMTYPE_VALUE			BIT(0)
-
-#define COHERENCY_CONTROL_2_OFF			0x8E4
-#define COHERENCY_CONTROL_3_OFF			0x8E8
-
-#define PCIE_PORT_MULTI_LANE_CTRL	0x8C0
-#define PORT_MLTI_UPCFG_SUPPORT		BIT(7)
-
-#define PCIE_VERSION_NUMBER		0x8F8
-#define PCIE_VERSION_TYPE		0x8FC
+#define TIMER_CTRL_MAX_FUNC_NUM		0x718
+#define  PORT_FLT_SF_MASK		GENMASK(30, 29)
+#define  PORT_FLT_SF_VAL_1024		0x0
+#define  PORT_FLT_SF_VAL_256		0x1
+#define  PORT_FLT_SF_VAL_64		0x2
+#define  PORT_FLT_SF_VAL_16		0x3
+
+#define PORT_LINK_DEBUG0		0x728		/* Port Link Debug Register 0 */
+#define  PORT_LINK_DEBUG0_LTSSM_MASK	0x3f		/* LTSSM current state mask */
+#define PORT_LINK_DEBUG1		0x72C		/* Port Link Debug Register 1 */
+#define  PORT_LINK_DEBUG1_LINK_UP		BIT(4)	/* LTSSM reports PHY link up or LTSSM is in Loopback */
+#define  PORT_LINK_DEBUG1_LINK_IN_TRAINING	BIT(29) /* LTSSM performing link training */
+
+#define LINK_WIDTH_SPEED_CTRL		0x80C		/* Link Width and Speed Change Control */
+#define  N_FTS_MASK			GENMASK(7, 0)
+#define  SPEED_CHANGE			BIT(17)
+#define  LINK_WIDTH_MASK		GENMASK(12, 8)
+#define  LINK_WIDTH(n)			FIELD_PREP(LINK_WIDTH_MASK, n)
+#define  LINK_WIDTH_1_LANES		LINK_WIDTH(0x1)
+#define  LINK_WIDTH_2_LANES		LINK_WIDTH(0x2)
+#define  LINK_WIDTH_4_LANES		LINK_WIDTH(0x4)
+#define  LINK_WIDTH_8_LANES		LINK_WIDTH(0x8)
+
+#define PCIE_MSI_ADDR_LO		0x820		/* Integrated MSI Reception Module Lower Address */
+#define PCIE_MSI_ADDR_HI		0x824		/* Integrated MSI Reception Module Upper Address */
+#define PCIE_MSI_INTR0_ENABLE		0x828		/* Integrated MSI Reception Module Interrupt0 Enable */
+#define PCIE_MSI_INTR0_MASK		0x82C		/* Integrated MSI Reception Module Interrupt0 Mask */
+#define PCIE_MSI_INTR0_STATUS		0x830		/* Integrated MSI Reception Module Interrupt0 Status */
+
+#define GEN3_CTRL			0x890		/* Gen3 Control Register */
+#define  GEN3_CTRL_GEN3_ZRXDC_NONCOMPL	BIT(0)		/* Gen3 Receiver Impedance ZRX-DC Not Compliant */
+#define  GEN3_CTRL_EQ_PHASE_2_3		BIT(9)		/* Equalization Phase 2 and Phase 3 */
+#define  GEN3_CTRL_RXEQ_RGRDLESS_RXTS	BIT(13)
+#define  GEN3_CTRL_GEN3_EQ_DISABLE	BIT(16)		/* Equalization Disable */
+#define  GEN3_CTRL_RATE_SHADOW_SEL_SHIFT 24		/* Rate Shadow Select shift */
+#define  GEN3_CTRL_RATE_SHADOW_SEL_MASK	GENMASK(25, 24)	/* Rate Shadow Select mask */
+
+#define GEN3_EQ_CTRL			0x8A8		/* Gen3 EQ Control */
+#define  GEN3_EQ_CTRL_FB_MODE		GENMASK(3, 0)	/* Feedback Mode */
+#define  GEN3_EQ_CTRL_PHASE23_EXIT_MODE	BIT(4)		/* Behavior After 24 ms Timeout */
+#define  GEN3_EQ_CTRL_PSET_REQ_VEC	GENMASK(23, 8)	/* Preset Request Vector */
+#define  GEN3_EQ_CTRL_FOM_INC_INITIAL_EVAL	BIT(24)	/* Include or not the FOM feedback from the initial preset */
+
+#define GEN3_EQ_FB_MODE_DIR_CHANGE		0x8AC	/* Gen3 EQ Direction Change Feedback Mode Control */
+#define  GEN3_EQ_FMDC_T_MIN_PHASE23		GENMASK(4, 0)
+#define  GEN3_EQ_FMDC_N_EVALS			GENMASK(9, 5)
+#define  GEN3_EQ_FMDC_MAX_PRE_CURSOR_DELTA	GENMASK(13, 10)
+#define  GEN3_EQ_FMDC_MAX_POST_CURSOR_DELTA	GENMASK(17, 14)
+
+#define MISC_CONTROL_1			0x8BC		/* DBI Read-Only Write Enable */
+#define  DBI_RO_WR_EN			BIT(0)		/* Write to RO Registers Using DBI */
+
+#define COHERENCY_CTRL1				0x8E0	/* Cache Coherency Control Register 1 */
+#define  CFG_MEMTYPE_BOUNDARY_LOW_ADDR_MASK	GENMASK(31, 2)	/* Boundary Lower Address For Memory Type */
+#define  CFG_MEMTYPE_VALUE			BIT(0)	/* Sets the memory type */
+
+#define COHERENCY_CTRL2				0x8E4	/* Cache Coherency Control Register 2 */
+#define COHERENCY_CTRL3				0x8E8	/* Cache Coherency Control Register 3 */
+
+#define MULTI_LANE_CTRL			0x8C0	/* UpConfigure Multi-lane Control */
+#define  MULTI_LANE_CTRL_UPCFG_SUPPORT	BIT(7)	/* Upconfigure Support */
+
+#define PCIE_VERSION_NUMBER		0x8F8	/* PCIe Controller IIP Release Version Number */
+#define PCIE_VERSION_TYPE		0x8FC	/* PCIe Controller IIP Release Version Type */
 
 /*
  * iATU inbound and outbound windows CSRs. Before the IP-core v4.80a each
@@ -186,38 +188,35 @@
  * v4.80a in a way so the viewport was unrolled into the directly accessible
  * iATU/eDMA CSRs space.
  */
-#define PCIE_ATU_VIEWPORT		0x900
-#define PCIE_ATU_REGION_DIR_IB		BIT(31)
-#define PCIE_ATU_REGION_DIR_OB		0
-#define PCIE_ATU_VIEWPORT_BASE		0x904
-#define PCIE_ATU_UNROLL_BASE(dir, index) \
-	(((index) << 9) | ((dir == PCIE_ATU_REGION_DIR_IB) ? BIT(8) : 0))
-#define PCIE_ATU_VIEWPORT_SIZE		0x2C
-#define PCIE_ATU_REGION_CTRL1		0x000
-#define PCIE_ATU_INCREASE_REGION_SIZE	BIT(13)
-#define PCIE_ATU_TD			BIT(8)
-#define PCIE_ATU_FUNC_NUM(pf)           ((pf) << 20)
-#define PCIE_ATU_REGION_CTRL2		0x004
-#define PCIE_ATU_ENABLE			BIT(31)
-#define PCIE_ATU_BAR_MODE_ENABLE	BIT(30)
-#define PCIE_ATU_CFG_SHIFT_MODE_ENABLE	BIT(28)
-#define PCIE_ATU_INHIBIT_PAYLOAD	BIT(22)
-#define PCIE_ATU_FUNC_NUM_MATCH_EN      BIT(19)
-#define PCIE_ATU_LOWER_BASE		0x008
-#define PCIE_ATU_UPPER_BASE		0x00C
-#define PCIE_ATU_LIMIT			0x010
-#define PCIE_ATU_LOWER_TARGET		0x014
-#define PCIE_ATU_BUS(x)			FIELD_PREP(GENMASK(31, 24), x)
-#define PCIE_ATU_DEV(x)			FIELD_PREP(GENMASK(23, 19), x)
-#define PCIE_ATU_FUNC(x)		FIELD_PREP(GENMASK(18, 16), x)
-#define PCIE_ATU_UPPER_TARGET		0x018
-#define PCIE_ATU_UPPER_LIMIT		0x020
-
-#define PCIE_MISC_CONTROL_1_OFF		0x8BC
-#define PCIE_DBI_RO_WR_EN		BIT(0)
-
-#define PCIE_MSIX_DOORBELL		0x948
-#define PCIE_MSIX_DOORBELL_PF_SHIFT	24
+#define IATU_VIEWPORT			0x900	/* iATU Index */
+#define ATU_REGION_DIR_IB		BIT(31)
+#define ATU_REGION_DIR_OB		0
+#define ATU_VIEWPORT_BASE		0x904
+#define ATU_UNROLL_BASE(dir, index) \
+	(((index) << 9) | ((dir == ATU_REGION_DIR_IB) ? BIT(8) : 0))
+#define ATU_VIEWPORT_SIZE		0x2C
+#define ATU_REGION_CTRL1		0x000
+#define  ATU_INCREASE_REGION_SIZE	BIT(13)
+#define  ATU_TD				BIT(8)
+#define ATU_FUNC_NUM(pf)		((pf) << 20)
+#define ATU_REGION_CTRL2		0x004
+#define  ATU_ENABLE			BIT(31)
+#define  ATU_BAR_MODE_ENABLE		BIT(30)
+#define  ATU_CFG_SHIFT_MODE_ENABLE	BIT(28)
+#define  ATU_INHIBIT_PAYLOAD		BIT(22)
+#define  ATU_FUNC_NUM_MATCH_EN		BIT(19)
+#define ATU_LOWER_BASE			0x008
+#define ATU_UPPER_BASE			0x00C
+#define ATU_LIMIT			0x010
+#define ATU_LOWER_TARGET		0x014
+#define ATU_BUS(x)			FIELD_PREP(GENMASK(31, 24), x)
+#define ATU_DEV(x)			FIELD_PREP(GENMASK(23, 19), x)
+#define ATU_FUNC(x)			FIELD_PREP(GENMASK(18, 16), x)
+#define ATU_UPPER_TARGET		0x018
+#define ATU_UPPER_LIMIT			0x020
+
+#define MSIX_DOORBELL			0x948
+#define  MSIX_DOORBELL_PF_SHIFT		24
 
 /*
  * eDMA CSRs. DW PCIe IP-core v4.70a and older had the eDMA registers accessible
@@ -274,7 +273,7 @@
 /*
  * RAS-DES register definitions
  */
-#define PCIE_RAS_DES_EVENT_COUNTER_CONTROL	0x8
+#define RAS_DES_EVENT_COUNTER_CONTROL	0x8
 #define EVENT_COUNTER_ALL_CLEAR		0x3
 #define EVENT_COUNTER_ENABLE_ALL	0x7
 #define EVENT_COUNTER_ENABLE_SHIFT	2
@@ -288,7 +287,7 @@
 #define EVENT_COUNTER_GROUP_SEL_SHIFT	24
 #define EVENT_COUNTER_GROUP_5		0x5
 
-#define PCIE_RAS_DES_EVENT_COUNTER_DATA		0xc
+#define RAS_DES_EVENT_COUNTER_DATA	0xc
 
 /* PTM register definitions */
 #define PTM_RES_REQ_CTRL		0x8
@@ -376,7 +375,7 @@ enum dw_pcie_core_rst {
 };
 
 enum dw_pcie_ltssm {
-	/* Need to align with PCIE_PORT_DEBUG0 bits 0:5 */
+	/* Need to align with PORT_LINK_DEBUG0 bits 0:5 */
 	DW_PCIE_LTSSM_DETECT_QUIET = 0x0,
 	DW_PCIE_LTSSM_DETECT_ACT = 0x1,
 	DW_PCIE_LTSSM_POLL_ACTIVE = 0x2,
@@ -813,9 +812,9 @@ static inline void dw_pcie_dbi_ro_wr_en(struct dw_pcie *pci)
 	u32 reg;
 	u32 val;
 
-	reg = PCIE_MISC_CONTROL_1_OFF;
+	reg = MISC_CONTROL_1;
 	val = dw_pcie_readl_dbi(pci, reg);
-	val |= PCIE_DBI_RO_WR_EN;
+	val |= DBI_RO_WR_EN;
 	dw_pcie_writel_dbi(pci, reg, val);
 }
 
@@ -824,9 +823,9 @@ static inline void dw_pcie_dbi_ro_wr_dis(struct dw_pcie *pci)
 	u32 reg;
 	u32 val;
 
-	reg = PCIE_MISC_CONTROL_1_OFF;
+	reg = MISC_CONTROL_1;
 	val = dw_pcie_readl_dbi(pci, reg);
-	val &= ~PCIE_DBI_RO_WR_EN;
+	val &= ~DBI_RO_WR_EN;
 	dw_pcie_writel_dbi(pci, reg, val);
 }
 
@@ -851,9 +850,9 @@ static inline enum dw_pcie_ltssm dw_pcie_get_ltssm(struct dw_pcie *pci)
 	if (pci->ops && pci->ops->get_ltssm)
 		return pci->ops->get_ltssm(pci);
 
-	val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0);
+	val = dw_pcie_readl_dbi(pci, PORT_LINK_DEBUG0);
 
-	return (enum dw_pcie_ltssm)FIELD_GET(PORT_LOGIC_LTSSM_STATE_MASK, val);
+	return (enum dw_pcie_ltssm)FIELD_GET(PORT_LINK_DEBUG0_LTSSM_MASK, val);
 }
 
 const char *dw_pcie_ltssm_status_string(enum dw_pcie_ltssm ltssm);
diff --git a/drivers/pci/controller/dwc/pcie-fu740.c b/drivers/pci/controller/dwc/pcie-fu740.c
index d0a34f680397..6c7ce1603170 100644
--- a/drivers/pci/controller/dwc/pcie-fu740.c
+++ b/drivers/pci/controller/dwc/pcie-fu740.c
@@ -215,9 +215,9 @@ static int fu740_pcie_start_link(struct dw_pcie *pci)
 		tmp |= orig;
 		dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_LNKCAP, tmp);
 
-		tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
-		tmp |= PORT_LOGIC_SPEED_CHANGE;
-		dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
+		tmp = dw_pcie_readl_dbi(pci, LINK_WIDTH_SPEED_CTRL);
+		tmp |= SPEED_CHANGE;
+		dw_pcie_writel_dbi(pci, LINK_WIDTH_SPEED_CTRL, tmp);
 
 		ret = dw_pcie_wait_for_link(pci);
 		if (ret) {
diff --git a/drivers/pci/controller/dwc/pcie-nxp-s32g.c b/drivers/pci/controller/dwc/pcie-nxp-s32g.c
index 31e1169b8ab6..386e44dd0477 100644
--- a/drivers/pci/controller/dwc/pcie-nxp-s32g.c
+++ b/drivers/pci/controller/dwc/pcie-nxp-s32g.c
@@ -107,7 +107,7 @@ static void s32g_pcie_reset_mstr_ace(struct dw_pcie *pci)
 	u32 ddr_base_high = upper_32_bits(S32G_MEMORY_BOUNDARY_ADDR);
 
 	dw_pcie_dbi_ro_wr_en(pci);
-	dw_pcie_writel_dbi(pci, COHERENCY_CONTROL_3_OFF, 0x0);
+	dw_pcie_writel_dbi(pci, COHERENCY_CTRL3, 0x0);
 
 	/*
 	 * Ncore is a cache-coherent interconnect module that enables the
@@ -125,9 +125,9 @@ static void s32g_pcie_reset_mstr_ace(struct dw_pcie *pci)
 	 * Define the start of DDR as seen by Linux as this boundary between
 	 * "memory" and "peripherals", with peripherals being below.
 	 */
-	dw_pcie_writel_dbi(pci, COHERENCY_CONTROL_1_OFF,
+	dw_pcie_writel_dbi(pci, COHERENCY_CTRL1,
 			   (ddr_base_low & CFG_MEMTYPE_BOUNDARY_LOW_ADDR_MASK));
-	dw_pcie_writel_dbi(pci, COHERENCY_CONTROL_2_OFF, ddr_base_high);
+	dw_pcie_writel_dbi(pci, COHERENCY_CTRL2, ddr_base_high);
 	dw_pcie_dbi_ro_wr_dis(pci);
 }
 
@@ -154,13 +154,13 @@ static int s32g_init_pcie_controller(struct dw_pcie_rp *pp)
 
 	dw_pcie_dbi_ro_wr_en(pci);
 
-	val = dw_pcie_readl_dbi(pci, PCIE_PORT_FORCE);
-	val |= PORT_FORCE_DO_DESKEW_FOR_SRIS;
-	dw_pcie_writel_dbi(pci, PCIE_PORT_FORCE, val);
+	val = dw_pcie_readl_dbi(pci, PORT_FORCE_LINK);
+	val |= PORT_FORCE_LINK_DDFS;
+	dw_pcie_writel_dbi(pci, PORT_FORCE_LINK, val);
 
-	val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
-	val |= GEN3_RELATED_OFF_EQ_PHASE_2_3;
-	dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
+	val = dw_pcie_readl_dbi(pci, GEN3_CTRL);
+	val |= GEN3_CTRL_EQ_PHASE_2_3;
+	dw_pcie_writel_dbi(pci, GEN3_CTRL, val);
 
 	dw_pcie_dbi_ro_wr_dis(pci);
 
diff --git a/drivers/pci/controller/dwc/pcie-qcom-common.c b/drivers/pci/controller/dwc/pcie-qcom-common.c
index 0da73caf2011..0b39648d2214 100644
--- a/drivers/pci/controller/dwc/pcie-qcom-common.c
+++ b/drivers/pci/controller/dwc/pcie-qcom-common.c
@@ -15,9 +15,9 @@ void qcom_pcie_common_set_equalization(struct dw_pcie *pci)
 	u16 speed;
 
 	/*
-	 * GEN3_RELATED_OFF register is repurposed to apply equalization
+	 * GEN3_CTRL register is repurposed to apply equalization
 	 * settings at various data transmission rates through registers namely
-	 * GEN3_EQ_*. The RATE_SHADOW_SEL bit field of GEN3_RELATED_OFF
+	 * GEN3_EQ_*. The RATE_SHADOW_SEL bit field of GEN3_CTRL
 	 * determines the data rate for which these equalization settings are
 	 * applied.
 	 */
@@ -28,25 +28,25 @@ void qcom_pcie_common_set_equalization(struct dw_pcie *pci)
 			break;
 		}
 
-		reg = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
-		reg &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL;
-		FIELD_MODIFY(GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK, &reg,
+		reg = dw_pcie_readl_dbi(pci, GEN3_CTRL);
+		reg &= ~GEN3_CTRL_GEN3_ZRXDC_NONCOMPL;
+		FIELD_MODIFY(GEN3_CTRL_RATE_SHADOW_SEL_MASK, &reg,
 			     speed - PCIE_SPEED_8_0GT);
-		dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, reg);
+		dw_pcie_writel_dbi(pci, GEN3_CTRL, reg);
 
-		reg = dw_pcie_readl_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF);
+		reg = dw_pcie_readl_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE);
 		FIELD_MODIFY(GEN3_EQ_FMDC_T_MIN_PHASE23, &reg, 0x1);
 		FIELD_MODIFY(GEN3_EQ_FMDC_N_EVALS, &reg, 0xd);
 		FIELD_MODIFY(GEN3_EQ_FMDC_MAX_PRE_CURSOR_DELTA, &reg, 0x5);
 		FIELD_MODIFY(GEN3_EQ_FMDC_MAX_POST_CURSOR_DELTA, &reg, 0x5);
-		dw_pcie_writel_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF, reg);
+		dw_pcie_writel_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE, reg);
 
-		reg = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF);
-		reg &= ~(GEN3_EQ_CONTROL_OFF_FB_MODE |
-			GEN3_EQ_CONTROL_OFF_PHASE23_EXIT_MODE |
-			GEN3_EQ_CONTROL_OFF_FOM_INC_INITIAL_EVAL |
-			GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC);
-		dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, reg);
+		reg = dw_pcie_readl_dbi(pci, GEN3_EQ_CTRL);
+		reg &= ~(GEN3_EQ_CTRL_FB_MODE |
+			GEN3_EQ_CTRL_PHASE23_EXIT_MODE |
+			GEN3_EQ_CTRL_FOM_INC_INITIAL_EVAL |
+			GEN3_EQ_CTRL_PSET_REQ_VEC);
+		dw_pcie_writel_dbi(pci, GEN3_EQ_CTRL, reg);
 	}
 }
 EXPORT_SYMBOL_GPL(qcom_pcie_common_set_equalization);
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index b58a607b713f..5dd5e9cec4ad 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -1295,9 +1295,9 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie)
 	writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE);
 	writel(BYPASS | MSTR_AXI_CLK_EN | AHB_CLK_EN,
 		pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
-	writel(GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS |
-		GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL,
-		pci->dbi_base + GEN3_RELATED_OFF);
+	writel(GEN3_CTRL_RXEQ_RGRDLESS_RXTS |
+		GEN3_CTRL_GEN3_ZRXDC_NONCOMPL,
+		pci->dbi_base + GEN3_CTRL);
 
 	writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS |
 		SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS |
diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
index fbe465a29068..2751848e9603 100644
--- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c
+++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
@@ -122,17 +122,17 @@ static int rcar_gen4_pcie_speed_change(struct dw_pcie *dw)
 	u32 val;
 	int i;
 
-	val = dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL);
-	val &= ~PORT_LOGIC_SPEED_CHANGE;
-	dw_pcie_writel_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
+	val = dw_pcie_readl_dbi(dw, LINK_WIDTH_SPEED_CTRL);
+	val &= ~SPEED_CHANGE;
+	dw_pcie_writel_dbi(dw, LINK_WIDTH_SPEED_CTRL, val);
 
-	val = dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL);
-	val |= PORT_LOGIC_SPEED_CHANGE;
-	dw_pcie_writel_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
+	val = dw_pcie_readl_dbi(dw, LINK_WIDTH_SPEED_CTRL);
+	val |= SPEED_CHANGE;
+	dw_pcie_writel_dbi(dw, LINK_WIDTH_SPEED_CTRL, val);
 
 	for (i = 0; i < RCAR_NUM_SPEED_CHANGE_RETRIES; i++) {
-		val = dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL);
-		if (!(val & PORT_LOGIC_SPEED_CHANGE))
+		val = dw_pcie_readl_dbi(dw, LINK_WIDTH_SPEED_CTRL);
+		if (!(val & SPEED_CHANGE))
 			return 0;
 		usleep_range(10000, 11000);
 	}
@@ -688,11 +688,11 @@ static void rcar_gen4_pcie_additional_common_init(struct rcar_gen4_pcie *rcar)
 	struct dw_pcie *dw = &rcar->dw;
 	u32 val;
 
-	val = dw_pcie_readl_dbi(dw, PCIE_PORT_LANE_SKEW);
+	val = dw_pcie_readl_dbi(dw, PORT_LANE_SKEW);
 	val &= ~PORT_LANE_SKEW_INSERT_MASK;
 	if (dw->num_lanes < 4)
 		val |= BIT(6);
-	dw_pcie_writel_dbi(dw, PCIE_PORT_LANE_SKEW, val);
+	dw_pcie_writel_dbi(dw, PORT_LANE_SKEW, val);
 
 	val = readl(rcar->base + PCIEPWRMNGCTRL);
 	val |= APP_CLK_REQ_N | APP_CLK_PM_EN;
@@ -803,9 +803,9 @@ static int rcar_gen4_pcie_ltssm_control(struct rcar_gen4_pcie *rcar, bool enable
 		return 0;
 	}
 
-	val = dw_pcie_readl_dbi(dw, PCIE_PORT_FORCE);
-	val |= PORT_FORCE_DO_DESKEW_FOR_SRIS;
-	dw_pcie_writel_dbi(dw, PCIE_PORT_FORCE, val);
+	val = dw_pcie_readl_dbi(dw, PORT_FORCE_LINK);
+	val |= PORT_FORCE_LINK_DDFS;
+	dw_pcie_writel_dbi(dw, PORT_FORCE_LINK, val);
 
 	val = readl(rcar->base + PCIEMSR0);
 	val |= APP_SRIS_MODE;
diff --git a/drivers/pci/controller/dwc/pcie-tegra194-acpi.c b/drivers/pci/controller/dwc/pcie-tegra194-acpi.c
index 2d737b49ea8f..352591dcef83 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194-acpi.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194-acpi.c
@@ -39,8 +39,8 @@ static int tegra194_acpi_init(struct pci_config_window *cfg)
 static void atu_reg_write(struct tegra194_pcie_ecam *pcie_ecam, int index,
 			  u32 val, u32 reg)
 {
-	u32 offset = PCIE_ATU_UNROLL_BASE(PCIE_ATU_REGION_DIR_OB, index) +
-		     PCIE_ATU_VIEWPORT_BASE;
+	u32 offset = ATU_UNROLL_BASE(ATU_REGION_DIR_OB, index) +
+		     ATU_VIEWPORT_BASE;
 
 	writel(val, pcie_ecam->iatu_base + offset + reg);
 }
@@ -50,17 +50,17 @@ static void program_outbound_atu(struct tegra194_pcie_ecam *pcie_ecam,
 				 u64 pci_addr, u64 size)
 {
 	atu_reg_write(pcie_ecam, index, lower_32_bits(cpu_addr),
-		      PCIE_ATU_LOWER_BASE);
+		      ATU_LOWER_BASE);
 	atu_reg_write(pcie_ecam, index, upper_32_bits(cpu_addr),
-		      PCIE_ATU_UPPER_BASE);
+		      ATU_UPPER_BASE);
 	atu_reg_write(pcie_ecam, index, lower_32_bits(pci_addr),
-		      PCIE_ATU_LOWER_TARGET);
+		      ATU_LOWER_TARGET);
 	atu_reg_write(pcie_ecam, index, lower_32_bits(cpu_addr + size - 1),
-		      PCIE_ATU_LIMIT);
+		      ATU_LIMIT);
 	atu_reg_write(pcie_ecam, index, upper_32_bits(pci_addr),
-		      PCIE_ATU_UPPER_TARGET);
-	atu_reg_write(pcie_ecam, index, type, PCIE_ATU_REGION_CTRL1);
-	atu_reg_write(pcie_ecam, index, PCIE_ATU_ENABLE, PCIE_ATU_REGION_CTRL2);
+		      ATU_UPPER_TARGET);
+	atu_reg_write(pcie_ecam, index, type, ATU_REGION_CTRL1);
+	atu_reg_write(pcie_ecam, index, ATU_ENABLE, ATU_REGION_CTRL2);
 }
 
 static void __iomem *tegra194_map_bus(struct pci_bus *bus,
@@ -81,8 +81,8 @@ static void __iomem *tegra194_map_bus(struct pci_bus *bus,
 			return NULL;
 	}
 
-	busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
-		 PCIE_ATU_FUNC(PCI_FUNC(devfn));
+	busdev = ATU_BUS(bus->number) | ATU_DEV(PCI_SLOT(devfn)) |
+		 ATU_FUNC(PCI_FUNC(devfn));
 
 	if (bus->parent->number == cfg->busr.start) {
 		if (PCI_SLOT(devfn) == 0)
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 63a0f56cad8e..8c610212a180 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -385,9 +385,9 @@ static irqreturn_t tegra_pcie_rp_irq_handler(int irq, void *arg)
 			val |= APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N;
 			appl_writel(pcie, val, APPL_CAR_RESET_OVRD);
 
-			val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
-			val |= PORT_LOGIC_SPEED_CHANGE;
-			dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
+			val = dw_pcie_readl_dbi(pci, LINK_WIDTH_SPEED_CTRL);
+			val |= SPEED_CHANGE;
+			dw_pcie_writel_dbi(pci, LINK_WIDTH_SPEED_CTRL, val);
 		}
 	}
 
@@ -621,15 +621,15 @@ static inline u32 event_counter_prog(struct tegra_pcie_dw *pcie, u32 event)
 	u32 val;
 
 	val = dw_pcie_readl_dbi(&pcie->pci, pcie->ras_des_cap +
-				PCIE_RAS_DES_EVENT_COUNTER_CONTROL);
+				RAS_DES_EVENT_COUNTER_CONTROL);
 	val &= ~(EVENT_COUNTER_EVENT_SEL_MASK << EVENT_COUNTER_EVENT_SEL_SHIFT);
 	val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT;
 	val |= event << EVENT_COUNTER_EVENT_SEL_SHIFT;
 	val |= EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT;
 	dw_pcie_writel_dbi(&pcie->pci, pcie->ras_des_cap +
-			   PCIE_RAS_DES_EVENT_COUNTER_CONTROL, val);
+			   RAS_DES_EVENT_COUNTER_CONTROL, val);
 	val = dw_pcie_readl_dbi(&pcie->pci, pcie->ras_des_cap +
-				PCIE_RAS_DES_EVENT_COUNTER_DATA);
+				RAS_DES_EVENT_COUNTER_DATA);
 
 	return val;
 }
@@ -657,14 +657,14 @@ static int aspm_state_cnt(struct seq_file *s, void *data)
 
 	/* Clear all counters */
 	dw_pcie_writel_dbi(&pcie->pci, pcie->ras_des_cap +
-			   PCIE_RAS_DES_EVENT_COUNTER_CONTROL,
+			   RAS_DES_EVENT_COUNTER_CONTROL,
 			   EVENT_COUNTER_ALL_CLEAR);
 
 	/* Re-enable counting */
 	val = EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT;
 	val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT;
 	dw_pcie_writel_dbi(&pcie->pci, pcie->ras_des_cap +
-			   PCIE_RAS_DES_EVENT_COUNTER_CONTROL, val);
+			   RAS_DES_EVENT_COUNTER_CONTROL, val);
 
 	return 0;
 }
@@ -683,7 +683,7 @@ static void init_host_aspm(struct tegra_pcie_dw *pcie)
 	val = EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT;
 	val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT;
 	dw_pcie_writel_dbi(pci, pcie->ras_des_cap +
-			   PCIE_RAS_DES_EVENT_COUNTER_CONTROL, val);
+			   RAS_DES_EVENT_COUNTER_CONTROL, val);
 
 	/* Program T_cmrt and T_pwr_on values */
 	val = dw_pcie_readl_dbi(pci, l1ss + PCI_L1SS_CAP);
@@ -713,13 +713,13 @@ static void init_host_aspm(struct tegra_pcie_dw *pcie)
 	}
 
 	/* Program L0s and L1 entrance latencies */
-	val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR);
-	val &= ~PORT_AFR_L0S_ENTRANCE_LAT_MASK;
-	val |= (pcie->aspm_l0s_enter_lat << PORT_AFR_L0S_ENTRANCE_LAT_SHIFT);
-	val &= ~PORT_AFR_L1_ENTRANCE_LAT_MASK;
-	val |= (pcie->aspm_l1_enter_lat << PORT_AFR_L1_ENTRANCE_LAT_SHIFT);
-	val |= PORT_AFR_ENTER_ASPM;
-	dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val);
+	val = dw_pcie_readl_dbi(pci, PORT_AFAC);
+	val &= ~PORT_AFAC_L0S_ELM;
+	val |= (pcie->aspm_l0s_enter_lat << PORT_AFAC_L0S_ELS);
+	val &= ~PORT_AFAC_L1_ELM;
+	val |= (pcie->aspm_l1_enter_lat << PORT_AFAC_L1_ELS);
+	val |= PORT_AFAC_ENTER_ASPM;
+	dw_pcie_writel_dbi(pci, PORT_AFAC, val);
 }
 
 static void init_debugfs(struct tegra_pcie_dw *pcie)
@@ -870,29 +870,29 @@ static void config_gen3_gen4_eq_presets(struct tegra_pcie_dw *pcie)
 		dw_pcie_writeb_dbi(pci, offset + i, val);
 	}
 
-	val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
-	val &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK;
-	dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
+	val = dw_pcie_readl_dbi(pci, GEN3_CTRL);
+	val &= ~GEN3_CTRL_RATE_SHADOW_SEL_MASK;
+	dw_pcie_writel_dbi(pci, GEN3_CTRL, val);
 
-	val = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF);
-	FIELD_MODIFY(GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC, &val, 0x3ff);
-	val &= ~GEN3_EQ_CONTROL_OFF_FB_MODE;
-	dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val);
+	val = dw_pcie_readl_dbi(pci, GEN3_EQ_CTRL);
+	FIELD_MODIFY(GEN3_EQ_CTRL_PSET_REQ_VEC, &val, 0x3ff);
+	val &= ~GEN3_EQ_CTRL_FB_MODE;
+	dw_pcie_writel_dbi(pci, GEN3_EQ_CTRL, val);
 
-	val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
-	val &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK;
-	val |= (0x1 << GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT);
-	dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
+	val = dw_pcie_readl_dbi(pci, GEN3_CTRL);
+	val &= ~GEN3_CTRL_RATE_SHADOW_SEL_MASK;
+	val |= (0x1 << GEN3_CTRL_RATE_SHADOW_SEL_SHIFT);
+	dw_pcie_writel_dbi(pci, GEN3_CTRL, val);
 
-	val = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF);
-	FIELD_MODIFY(GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC, &val,
+	val = dw_pcie_readl_dbi(pci, GEN3_EQ_CTRL);
+	FIELD_MODIFY(GEN3_EQ_CTRL_PSET_REQ_VEC, &val,
 		     pcie->of_data->gen4_preset_vec);
-	val &= ~GEN3_EQ_CONTROL_OFF_FB_MODE;
-	dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val);
+	val &= ~GEN3_EQ_CTRL_FB_MODE;
+	dw_pcie_writel_dbi(pci, GEN3_EQ_CTRL, val);
 
-	val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
-	val &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK;
-	dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
+	val = dw_pcie_readl_dbi(pci, GEN3_CTRL);
+	val &= ~GEN3_CTRL_RATE_SHADOW_SEL_MASK;
+	dw_pcie_writel_dbi(pci, GEN3_CTRL, val);
 }
 
 static int tegra_pcie_dw_host_init(struct dw_pcie_rp *pp)
@@ -940,9 +940,9 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *pp)
 	init_host_aspm(pcie);
 
 	if (!pcie->of_data->has_l1ss_exit_fix) {
-		val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
-		val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL;
-		dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
+		val = dw_pcie_readl_dbi(pci, GEN3_CTRL);
+		val &= ~GEN3_CTRL_GEN3_ZRXDC_NONCOMPL;
+		dw_pcie_writel_dbi(pci, GEN3_CTRL, val);
 	}
 
 	if (pcie->update_fc_fixup) {
@@ -1869,9 +1869,9 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
 	pci_epc_deinit_notify(pcie->pci.ep.epc);
 	dw_pcie_ep_cleanup(&pcie->pci.ep);
 
-	val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
-	val &= ~PORT_LOGIC_SPEED_CHANGE;
-	dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
+	val = dw_pcie_readl_dbi(pci, LINK_WIDTH_SPEED_CTRL);
+	val &= ~SPEED_CHANGE;
+	dw_pcie_writel_dbi(pci, LINK_WIDTH_SPEED_CTRL, val);
 
 	if (pcie->update_fc_fixup) {
 		val = dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF);
@@ -1884,9 +1884,9 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
 	init_host_aspm(pcie);
 
 	if (!pcie->of_data->has_l1ss_exit_fix) {
-		val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
-		val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL;
-		dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
+		val = dw_pcie_readl_dbi(pci, GEN3_CTRL);
+		val &= ~GEN3_CTRL_GEN3_ZRXDC_NONCOMPL;
+		dw_pcie_writel_dbi(pci, GEN3_CTRL, val);
 	}
 
 	pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci,
diff --git a/drivers/pci/controller/dwc/pcie-ultrarisc.c b/drivers/pci/controller/dwc/pcie-ultrarisc.c
index 51e89180490d..a0d328c0c09b 100644
--- a/drivers/pci/controller/dwc/pcie-ultrarisc.c
+++ b/drivers/pci/controller/dwc/pcie-ultrarisc.c
@@ -52,18 +52,18 @@ static int ultrarisc_pcie_host_init(struct dw_pcie_rp *pp)
 	val &= ~FAST_LINK_MODE;
 	dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val);
 
-	val = dw_pcie_readl_dbi(pci, PCIE_TIMER_CTRL_MAX_FUNC_NUM);
+	val = dw_pcie_readl_dbi(pci, TIMER_CTRL_MAX_FUNC_NUM);
 	FIELD_MODIFY(PORT_FLT_SF_MASK, &val, PORT_FLT_SF_VAL_64);
-	dw_pcie_writel_dbi(pci, PCIE_TIMER_CTRL_MAX_FUNC_NUM, val);
+	dw_pcie_writel_dbi(pci, TIMER_CTRL_MAX_FUNC_NUM, val);
 
 	cap_exp = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
 	val = dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_LNKCTL2);
 	FIELD_MODIFY(PCI_EXP_LNKCTL2_TLS, &val, PCI_EXP_LNKCTL2_TLS_16_0GT);
 	dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_LNKCTL2, val);
 
-	val = dw_pcie_readl_dbi(pci, PCIE_PORT_FORCE);
-	FIELD_MODIFY(PORT_LINK_NUM_MASK, &val, 0);
-	dw_pcie_writel_dbi(pci, PCIE_PORT_FORCE, val);
+	val = dw_pcie_readl_dbi(pci, PORT_FORCE_LINK);
+	FIELD_MODIFY(PORT_FORCE_LINK_NUM_MASK, &val, 0);
+	dw_pcie_writel_dbi(pci, PORT_FORCE_LINK, val);
 
 	val = dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_DEVCTL2);
 	FIELD_MODIFY(PCI_EXP_DEVCTL2_COMP_TIMEOUT, &val,
-- 
2.34.1


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Re: [PATCH 1/2] PCI: dwc: Align register macros with Synopsys documentation

[sashiko-bot]

> The DWC PCIe register and field macros are inconsistently named and
> often do not match the Synopsys DesignWare PCIe Controller Reference
> Manual.  This makes it harder to cross-reference the code with the
> documentation when debugging or maintaining the driver.
> 
> As suggested during review, do not add an "_OFF" suffix to the Port Link
> Control register: the suffix is ambiguous (offset vs. off) and
> unnecessary.  Use PORT_LINK_CTRL, and include the register name in its
> field macros, e.g. PORT_LINK_CTRL_DLE, PORT_LINK_CTRL_FLM, and
> PORT_LINK_CTRL_LC_*.
> 
> Align other DWC PCIe controller-internal register macros in the same
> spirit by dropping the redundant PCIE_ prefix and using the documented
> base names, such as PORT_FORCE_LINK, PORT_AFAC, PORT_LANE_SKEW,
> TIMER_CTRL_MAX_FUNC_NUM, PORT_LINK_DEBUG0/1, LINK_WIDTH_SPEED_CTRL,
> GEN3_CTRL, GEN3_EQ_CTRL, MULTI_LANE_CTRL, MISC_CONTROL_1,
> MSIX_DOORBELL, and the ATU_* registers.  Field macros are renamed
> consistently so their register association is clear.
> 
> This improves code maintainability and eases future reference to the
> controller manual.
> 
> No functional change intended.
> 
> Co-developed-by: Feizhou Yu <yufeizhou201@163.com>
> Signed-off-by: Feizhou Yu <yufeizhou201@163.com>
> Signed-off-by: Hans Zhang <18255117159@163.com>

Sashiko has reviewed this patch and found no issues. It looks great!

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260911162537.469018-1-18255117159@163.com?part=1


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[PATCH 2/2] PCI: dwc: Remove unused PCIE_ATU_UNR_* register definitions

[Hans Zhang]

The PCIE_ATU_UNR_* macros are not used anywhere in the kernel.  They
were presumably intended for unrolled iATU register access, but the
driver now uses the ATU_* macros and computes unrolled offsets via
ATU_UNROLL_BASE().

Remove these unused definitions. No functional change intended.

Signed-off-by: Hans Zhang <18255117159@163.com>
---
 drivers/pci/controller/dwc/pcie-designware.h | 12 ------------
 1 file changed, 12 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 10bf06427e41..89cb809e056b 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -257,18 +257,6 @@
 #define MARGINING_MAXLANES			GENMASK(20, 16)
 #define MARGINING_SAMPLE_RATE_TIMING		GENMASK(13, 8)
 #define MARGINING_SAMPLE_RATE_VOLTAGE		GENMASK(5, 0)
-/*
- * iATU Unroll-specific register definitions
- * From 4.80 core version the address translation will be made by unroll
- */
-#define PCIE_ATU_UNR_REGION_CTRL1	0x00
-#define PCIE_ATU_UNR_REGION_CTRL2	0x04
-#define PCIE_ATU_UNR_LOWER_BASE		0x08
-#define PCIE_ATU_UNR_UPPER_BASE		0x0C
-#define PCIE_ATU_UNR_LOWER_LIMIT	0x10
-#define PCIE_ATU_UNR_LOWER_TARGET	0x14
-#define PCIE_ATU_UNR_UPPER_TARGET	0x18
-#define PCIE_ATU_UNR_UPPER_LIMIT	0x20
 
 /*
  * RAS-DES register definitions
-- 
2.34.1


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Re: [PATCH 2/2] PCI: dwc: Remove unused PCIE_ATU_UNR_* register definitions

[sashiko-bot]

> The PCIE_ATU_UNR_* macros are not used anywhere in the kernel.  They
> were presumably intended for unrolled iATU register access, but the
> driver now uses the ATU_* macros and computes unrolled offsets via
> ATU_UNROLL_BASE().
> 
> Remove these unused definitions. No functional change intended.
> 
> Signed-off-by: Hans Zhang <18255117159@163.com>

Sashiko has reviewed this patch and found no issues. It looks great!

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260911162537.469018-1-18255117159@163.com?part=2


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