From: Jian Hu via B4 Relay <devnull+jian.hu.amlogic.com@kernel.org>
To: Neil Armstrong <neil.armstrong@linaro.org>,
Jerome Brunet <jbrunet@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Brian Masney <bmasney+clk@redhat.com>,
Kevin Hilman <khilman@baylibre.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
Jerome Brunet <jbrunet+clk@baylibre.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
Jian Hu <jian.hu@amlogic.com>
Subject: [PATCH RFC 2/3] dt-bindings: clock: amlogic: Add T7 pre-divider clock IDs
Date: Wed, 23 Sep 2026 19:14:48 +0800 [thread overview]
Message-ID: <20260923-meson_refactor_n-v1-2-3a8ce27121a2@amlogic.com> (raw)
In-Reply-To: <20260923-meson_refactor_n-v1-0-3a8ce27121a2@amlogic.com>
From: Jian Hu <jian.hu@amlogic.com>
Add clock IDs for the T7 PLL pre-divider clocks. These IDs are
required for the subsequent conversion of the PLL pre-divider
into a standalone divider clock following the PLL framework refactoring.
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
---
include/dt-bindings/clock/amlogic,t7-pll-clkc.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/include/dt-bindings/clock/amlogic,t7-pll-clkc.h b/include/dt-bindings/clock/amlogic,t7-pll-clkc.h
index e2481f2f1163..69c90bc0be0a 100644
--- a/include/dt-bindings/clock/amlogic,t7-pll-clkc.h
+++ b/include/dt-bindings/clock/amlogic,t7-pll-clkc.h
@@ -9,20 +9,24 @@
/* GP0 */
#define CLKID_GP0_PLL_DCO 0
#define CLKID_GP0_PLL 1
+#define CLKID_GP0_PREDIV 2
/* GP1 */
#define CLKID_GP1_PLL_DCO 0
#define CLKID_GP1_PLL 1
+#define CLKID_GP1_PREDIV 2
/* HIFI */
#define CLKID_HIFI_PLL_DCO 0
#define CLKID_HIFI_PLL 1
+#define CLKID_HIFI_PREDIV 2
/* PCIE */
#define CLKID_PCIE_PLL_DCO 0
#define CLKID_PCIE_PLL_DCO_DIV2 1
#define CLKID_PCIE_PLL_OD 2
#define CLKID_PCIE_PLL 3
+#define CLKID_PCIE_PREDIV 4
/* MPLL */
#define CLKID_MPLL_PREDIV 0
@@ -39,6 +43,7 @@
#define CLKID_HDMI_PLL_DCO 0
#define CLKID_HDMI_PLL_OD 1
#define CLKID_HDMI_PLL 2
+#define CLKID_HDMI_PREDIV 3
/* MCLK */
#define CLKID_MCLK_PLL_DCO 0
@@ -52,5 +57,6 @@
#define CLKID_MCLK_1_DIV2 8
#define CLKID_MCLK_1_PRE 9
#define CLKID_MCLK_1 10
+#define CLKID_MCLK_PREDIV 11
#endif /* __T7_PLL_CLKC_H */
--
2.47.1
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next prev parent reply other threads:[~2026-09-23 11:15 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-23 11:14 [PATCH RFC 0/3] clk: meson: Refactor PLL pre-divider as a divider clock Jian Hu via B4 Relay
2026-09-23 11:14 ` [PATCH RFC 1/3] clk: meson: pll: Remove the dedicated n parameter Jian Hu via B4 Relay
2026-09-23 11:24 ` sashiko-bot
2026-09-24 10:36 ` Jian Hu
2026-09-23 11:14 ` Jian Hu via B4 Relay [this message]
2026-09-23 11:14 ` [PATCH RFC 3/3] clk: meson: t7: Model PLL pre-divider as a divider clock Jian Hu via B4 Relay
2026-09-23 11:26 ` sashiko-bot
2026-09-24 10:37 ` Jian Hu
2026-09-24 9:35 ` [PATCH RFC 0/3] clk: meson: Refactor " Jerome Brunet
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