From: Krzysztof Kozlowski <krzk@kernel.org>
To: christian.koever-draxl@student.uibk.ac.at
Cc: ulfh@kernel.org, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, neil.armstrong@linaro.org,
khilman@baylibre.com, jbrunet@baylibre.com,
martin.blumenstingl@googlemail.com, linux-mmc@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org,
"Christian Stefan Kövér-Draxl" <ckoever@outlook.de>
Subject: Re: [PATCH 1/2] dt-bindings: mmc: amlogic,meson-gx-mmc: add amlogic,core-phase-degrees
Date: Fri, 30 Oct 2026 12:21:41 +0100 [thread overview]
Message-ID: <20261030-sarcastic-sophisticated-tortoise-a7a8ea@quoll> (raw)
In-Reply-To: <20261025192059.208792-2-christian.koever-draxl@student.uibk.ac.at>
On Sun, Oct 25, 2026 at 08:20:58PM +0100, christian.koever-draxl@student.uibk.ac.at wrote:
> From: Christian Stefan Kövér-Draxl <ckoever@outlook.de>
>
> The controller samples with a core clock phase that is fixed at 180
> degrees in the driver. Some boards need another phase to work at high
> speed: an SD slot on an S905W2 TV box fails with CRC errors at 50 MHz
> at 180 degrees but works reliably at 270 degrees, which is also what
> the vendor kernel programs for it.
>
> Add an optional property to describe the phase.
>
> Signed-off-by: Christian Stefan Kövér-Draxl <ckoever@outlook.de>
> ---
> .../devicetree/bindings/mmc/amlogic,meson-gx-mmc.yaml | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx-mmc.yaml b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx-mmc.yaml
> index 976f36de2091..8123375a66e0 100644
> --- a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx-mmc.yaml
> +++ b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx-mmc.yaml
> @@ -58,6 +58,15 @@ properties:
> power-domains:
> maxItems: 1
>
> + amlogic,core-phase-degrees:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + Phase of the controller core clock relative to the card clock. Some
> + boards only sample reliably at high speed with a phase other than
> + the default.
> + enum: [0, 90, 180, 270]
> + default: 180
Is this the same as clk-phase- properties from mmc schema?
Best regards,
Krzysztof
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next prev parent reply other threads:[~2026-10-30 11:21 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-25 19:20 [PATCH 0/2] mmc: meson-gx: make the core clock phase configurable christian.koever-draxl
2026-10-25 19:20 ` [PATCH 1/2] dt-bindings: mmc: amlogic,meson-gx-mmc: add amlogic,core-phase-degrees christian.koever-draxl
2026-10-30 11:21 ` Krzysztof Kozlowski [this message]
2026-10-25 19:20 ` [PATCH 2/2] mmc: meson-gx: allow the core clock phase to be set from DT christian.koever-draxl
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