[PATCH 0/2] mmc: meson-gx: make the core clock phase configurable

[PATCH 0/2] mmc: meson-gx: make the core clock phase configurable

[christian.koever-draxl]

From: Christian Stefan Kövér-Draxl <ckoever@outlook.de>

The core clock phase is fixed at 180 degrees. The SD slot of an S905W2
TV box fails with CRC errors at 50 MHz with that phase and works at 270
degrees, the value the vendor kernel programs. Add an optional DT
property for it and keep 180 degrees as the default.

Tool use (Documentation/process/generated-content.rst):
This work was done with the help of an AI coding assistant, Claude
(Anthropic), used through Claude Code over many sessions. It did a large
part of the hands-on work: it read the vendor kernel and the firmware
interfaces, probed registers on the board, drafted the code and the
changelogs, and ran the builds, checkpatch, dt_binding_check and the
tests on the hardware. I directed the work, reviewed every change and
the final patches, and take responsibility for them. There is no single
prompt to quote; the sessions were of the form "find out why X fails on
this board, fix it, test it on the box".

Tested on an Amediatech X98Q TV box (Amlogic S905W2, S4 family, 2 GiB),
vendor U-Boot and BL31/OP-TEE, Linux 7.3 plus this work.

Christian Stefan Kövér-Draxl (2):
  dt-bindings: mmc: amlogic,meson-gx-mmc: add amlogic,core-phase-degrees
  mmc: meson-gx: allow the core clock phase to be set from DT

 .../bindings/mmc/amlogic,meson-gx-mmc.yaml      |  9 +++++++++
 drivers/mmc/host/meson-gx-mmc.c                 | 17 +++++++++++++++--
 2 files changed, 24 insertions(+), 2 deletions(-)


base-commit: 7be4bc52fd9e0e55dc9a2e0232b89427d2c4b614
-- 
2.56.0


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[PATCH 1/2] dt-bindings: mmc: amlogic,meson-gx-mmc: add amlogic,core-phase-degrees

[christian.koever-draxl]

From: Christian Stefan Kövér-Draxl <ckoever@outlook.de>

The controller samples with a core clock phase that is fixed at 180
degrees in the driver. Some boards need another phase to work at high
speed: an SD slot on an S905W2 TV box fails with CRC errors at 50 MHz
at 180 degrees but works reliably at 270 degrees, which is also what
the vendor kernel programs for it.

Add an optional property to describe the phase.

Signed-off-by: Christian Stefan Kövér-Draxl <ckoever@outlook.de>
---
 .../devicetree/bindings/mmc/amlogic,meson-gx-mmc.yaml    | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx-mmc.yaml b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx-mmc.yaml
index 976f36de2091..8123375a66e0 100644
--- a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx-mmc.yaml
+++ b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx-mmc.yaml
@@ -58,6 +58,15 @@ properties:
   power-domains:
     maxItems: 1
 
+  amlogic,core-phase-degrees:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Phase of the controller core clock relative to the card clock. Some
+      boards only sample reliably at high speed with a phase other than
+      the default.
+    enum: [0, 90, 180, 270]
+    default: 180
+
 required:
   - compatible
   - reg
-- 
2.56.0


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[PATCH 2/2] mmc: meson-gx: allow the core clock phase to be set from DT

[christian.koever-draxl]

From: Christian Stefan Kövér-Draxl <ckoever@outlook.de>

The core phase is hardcoded to 180 degrees. On an S905W2 board the SD
card fails with CRC errors (-EILSEQ) right after switching to high
speed at 50 MHz.

Sweeping the core phase on the live controller showed that 270 degrees
works on that slot, as the vendor kernel's init_core_phase setting
does. With it the card runs at 50 MHz: 21.7 MB/s sequential read,
6.3 MB/s write, data verified by checksum.

Read the optional amlogic,core-phase-degrees property and keep 180
degrees as the default.

Signed-off-by: Christian Stefan Kövér-Draxl <ckoever@outlook.de>
---
 drivers/mmc/host/meson-gx-mmc.c | 17 +++++++++++++++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
index 694bb443d5f3..42c855248675 100644
--- a/drivers/mmc/host/meson-gx-mmc.c
+++ b/drivers/mmc/host/meson-gx-mmc.c
@@ -425,12 +425,25 @@ static int meson_mmc_clk_init(struct meson_host *host)
 	int i, ret = 0;
 	const char *mux_parent_names[MUX_CLK_NUM_PARENTS];
 	const char *clk_parent[1];
-	u32 clk_reg;
+	u32 clk_reg, core_phase = 180;
+
+	/*
+	 * 180 degrees suits most boards, but some only sample reliably at
+	 * high speed with another core phase (the vendor trees carry this as
+	 * "init_core_phase"). The field is in 90 degree steps.
+	 */
+	device_property_read_u32(host->dev, "amlogic,core-phase-degrees",
+				 &core_phase);
+	if (core_phase % 90 || core_phase > 270) {
+		dev_warn(host->dev, "invalid amlogic,core-phase-degrees %u, using 180\n",
+			 core_phase);
+		core_phase = 180;
+	}
 
 	/* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
 	clk_reg = CLK_ALWAYS_ON(host);
 	clk_reg |= CLK_DIV_MASK;
-	clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
+	clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, core_phase / 90);
 	clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0);
 	clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
 	if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
-- 
2.56.0


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Re: [PATCH 1/2] dt-bindings: mmc: amlogic,meson-gx-mmc: add amlogic,core-phase-degrees

[Krzysztof Kozlowski]

On Sun, Oct 25, 2026 at 08:20:58PM +0100, christian.koever-draxl@student.uibk.ac.at wrote:
> From: Christian Stefan Kövér-Draxl <ckoever@outlook.de>
> 
> The controller samples with a core clock phase that is fixed at 180
> degrees in the driver. Some boards need another phase to work at high
> speed: an SD slot on an S905W2 TV box fails with CRC errors at 50 MHz
> at 180 degrees but works reliably at 270 degrees, which is also what
> the vendor kernel programs for it.
> 
> Add an optional property to describe the phase.
> 
> Signed-off-by: Christian Stefan Kövér-Draxl <ckoever@outlook.de>
> ---
>  .../devicetree/bindings/mmc/amlogic,meson-gx-mmc.yaml    | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx-mmc.yaml b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx-mmc.yaml
> index 976f36de2091..8123375a66e0 100644
> --- a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx-mmc.yaml
> +++ b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx-mmc.yaml
> @@ -58,6 +58,15 @@ properties:
>    power-domains:
>      maxItems: 1
>  
> +  amlogic,core-phase-degrees:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description:
> +      Phase of the controller core clock relative to the card clock. Some
> +      boards only sample reliably at high speed with a phase other than
> +      the default.
> +    enum: [0, 90, 180, 270]
> +    default: 180

Is this the same as clk-phase- properties from mmc schema?

Best regards,
Krzysztof


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