From: Conor Dooley <conor@kernel.org>
To: Carlo Caione <ccaione@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>,
Brian Masney <bmasney+clk@redhat.com>,
Jerome Brunet <jbrunet+clk@baylibre.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Neil Armstrong <neil.armstrong@linaro.org>,
Jerome Brunet <jbrunet@baylibre.com>,
Kevin Hilman <khilman@baylibre.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
Jian Hu <jian.hu@amlogic.com>, Chuan Liu <chuan.liu@amlogic.com>,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 6/7] dt-bindings: clock: Add Amlogic S7 peripherals clock controller
Date: Fri, 6 Nov 2026 20:48:01 +0000 [thread overview]
Message-ID: <20261106-headband-buckwheat-fecbd459ee85@spud> (raw)
In-Reply-To: <au4p0xYEFkgEU6T4@macbook>
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On Fri, Nov 06, 2026 at 08:34:37PM +0100, Carlo Caione wrote:
> On Fri, Nov 06, 2026 at 17:34:14 +0100, Conor Dooley wrote:
>
> > > + #include <dt-bindings/clock/amlogic,s7-pll-clkc.h>
> > > + #include <dt-bindings/clock/amlogic,s7-scmi-clkc.h>
> > > +
> > > + soc {
> > > + #address-cells = <2>;
> > > + #size-cells = <2>;
> > > +
> > > + clock-controller@0 {
> > > + compatible = "amlogic,s7-peripherals-clkc";
> > > + reg = <0x0 0x0 0x0 0x49c>;
> >
> > What's with the weird numbers in this example?
> >
> > Examples don't have to be real, but when it looks like this the
> > immediate thought is that the modelling of the device might be
> > incorrec.t
>
> The numbers are actually real, but the example simply lost their context
> because I copied the node from the S7 dtsi (not yet submitted), where
> the controller sits under the APB bus node (bus@fe000000) and the bus
> ranges make the addresses relative to it.
>
> apb: bus@fe000000 {
> compatible = "simple-bus";
> reg = <0x0 0xfe000000 0x0 0x480000>;
> #address-cells = <2>;
> #size-cells = <2>;
> ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
>
> clkc_periphs: clock-controller@0 {
> compatible = "amlogic,s7-peripherals-clkc";
> reg = <0x0 0x0 0x0 0x49c>;
> #clock-cells = <1>;
> ...
>
> In V2 I'll use an absolute address for the sake of clarity (PLL has the
> same issue).
Before you do that, can you please share with me the s7 dtsi? Cos surely
you've got it in some git repo online somewhere.
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next prev parent reply other threads:[~2026-11-06 20:48 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-06 8:30 [PATCH 0/7] Add Amlogic S7 clock controllers Carlo Caione
2026-11-06 8:30 ` [PATCH 1/7] dt-bindings: clock: Add Amlogic S7 SCMI clock IDs Carlo Caione
2026-11-06 8:30 ` [PATCH 2/7] clk: meson: pll: Support PLLs without a pre-divider Carlo Caione
2026-11-06 8:35 ` sashiko-bot
2026-11-06 8:30 ` [PATCH 3/7] clk: meson: pll: Support active-low resets Carlo Caione
2026-11-06 8:30 ` [PATCH 4/7] dt-bindings: clock: Add Amlogic S7 PLL clock controller Carlo Caione
2026-11-06 17:35 ` Conor Dooley
2026-11-06 8:30 ` [PATCH 5/7] clk: amlogic: Add S7 PLL clock controller driver Carlo Caione
2026-11-06 8:51 ` sashiko-bot
2026-11-06 8:30 ` [PATCH 6/7] dt-bindings: clock: Add Amlogic S7 peripherals clock controller Carlo Caione
2026-11-06 17:34 ` Conor Dooley
2026-11-06 19:34 ` Carlo Caione
2026-11-06 20:48 ` Conor Dooley [this message]
2026-11-06 8:30 ` [PATCH 7/7] clk: amlogic: Add S7 peripherals clock controller driver Carlo Caione
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