[GIT PULL] clk: meson: updates for v4.21

[GIT PULL] clk: meson: updates for v4.21

[Neil Armstrong]

Dear clock maintainers,

Below is a request to pull updates for Amlogic clocks.

It covers essentially Meson GX Video clocks, Meson8b CPU clocks
and 2 bindings changes.

Thanks,
Neil

The following changes since commit 651022382c7f8da46cb4872a545ee1da6d097d2a:

  Linux 4.20-rc1 (2018-11-04 15:37:52 -0800)

are available in the Git repository at:

  git://github.com/BayLibre/clk-meson.git tags/meson-clk-4.21-1

for you to fetch changes up to a7d19b05ce817d60ae672c4c112e77892978dc3c:

  clk: meson: meson8b: add the CPU clock post divider clocks (2018-11-23 15:11:58 +0100)

----------------------------------------------------------------
Update for meson clocks targeted at v4.21
- Add GX video clocks
- Switch to HHI syscon for meson8b
- Fix meson8b cpu clock
- Add support for meson8b CPU scaling
- Add Meson8b CPU post-dividers clocks

----------------------------------------------------------------
Martin Blumenstingl (14):
      dt-bindings: clock: meson8b: export the CPU post dividers
      dt-bindings: clock: meson8b: use the registers from the HHI syscon
      clk: meson: meson8b: use the HHI syscon if available
      clk: meson: meson8b: fix incorrect divider mapping in cpu_scale_table
      clk: meson: meson8b: fix the width of the cpu_scale_div clock
      clk: meson: clk-pll: check if the clock is already enabled
      clk: meson: meson8b: do not use cpu_div3 for cpu_scale_out_sel
      clk: meson: meson8b: mark the CPU clock as CLK_IS_CRITICAL
      clk: meson: meson8b: add support for more M/N values in sys_pll
      clk: meson: meson8b: run from the XTAL when changing the CPU frequency
      clk: meson: meson8b: allow changing the CPU clock tree
      clk: meson: clk-regmap: add read-only gate ops
      clk: meson: meson8b: rename cpu_div2/cpu_div3 to cpu_in_div2/cpu_in_div3
      clk: meson: meson8b: add the CPU clock post divider clocks

Neil Armstrong (4):
      clk: meson: Add vid_pll divider driver
      clk: meson-gxbb: Fix HDMI PLL for GXL SoCs
      dt-bindings: clk: meson-gxbb: Add Video clock bindings
      clk: meson-gxbb: Add video clocks

 .../bindings/clock/amlogic,meson8b-clkc.txt        |  13 +-
 drivers/clk/meson/Makefile                         |   2 +-
 drivers/clk/meson/clk-pll.c                        |  19 +
 drivers/clk/meson/clk-regmap.c                     |   5 +
 drivers/clk/meson/clk-regmap.h                     |   1 +
 drivers/clk/meson/clkc.h                           |   6 +
 drivers/clk/meson/gxbb.c                           | 773 ++++++++++++++++++++-
 drivers/clk/meson/gxbb.h                           |  26 +-
 drivers/clk/meson/meson8b.c                        | 393 ++++++++++-
 drivers/clk/meson/meson8b.h                        |  17 +-
 drivers/clk/meson/vid-pll-div.c                    |  91 +++
 include/dt-bindings/clock/gxbb-clkc.h              |  18 +
 include/dt-bindings/clock/meson8b-clkc.h           |   4 +
 13 files changed, 1319 insertions(+), 49 deletions(-)
 create mode 100644 drivers/clk/meson/vid-pll-div.c

[GIT PULL] clk: meson: updates for v4.21

[Stephen Boyd]

Quoting Neil Armstrong (2018-11-23 07:23:33)
> Dear clock maintainers,
> 
> Below is a request to pull updates for Amlogic clocks.
> 
> It covers essentially Meson GX Video clocks, Meson8b CPU clocks
> and 2 bindings changes.
> 
> Thanks,
> Neil
> 
> The following changes since commit 651022382c7f8da46cb4872a545ee1da6d097d2a:
> 
>   Linux 4.20-rc1 (2018-11-04 15:37:52 -0800)
> 
> are available in the Git repository at:
> 
>   git://github.com/BayLibre/clk-meson.git tags/meson-clk-4.21-1
> 
> for you to fetch changes up to a7d19b05ce817d60ae672c4c112e77892978dc3c:
> 
>   clk: meson: meson8b: add the CPU clock post divider clocks (2018-11-23 15:11:58 +0100)
> 
> ----------------------------------------------------------------
> Update for meson clocks targeted at v4.21
> - Add GX video clocks
> - Switch to HHI syscon for meson8b

This never seemed to be resolved on the mailing list. I'm still waiting
to see what happens with the syscon and binding. I guess I need to look
at these PRs a little closer to make sure nothing else it outstanding on
the list.

> - Fix meson8b cpu clock
> - Add support for meson8b CPU scaling
> - Add Meson8b CPU post-dividers clocks

These other ones look OK.

Re: [GIT PULL] clk: meson: updates for v4.21

[Stephen Boyd]

Quoting Neil Armstrong (2018-11-23 07:23:33)
> Dear clock maintainers,
> 
> Below is a request to pull updates for Amlogic clocks.
> 
> It covers essentially Meson GX Video clocks, Meson8b CPU clocks
> and 2 bindings changes.

Pulled into clk-next now.

I got this when testing:

drivers/clk/meson/vid-pll-div.c:58:26: warning: symbol '_get_table_val' was not declared. Should it be static?
drivers/clk/meson/gxbb.c:1585:12: warning: symbol 'gxbb_vid_pll_parent_names' was not declared. Should it be static?
drivers/clk/meson/gxbb.c:1620:12: warning: symbol 'gxbb_vclk_parent_names' was not declared. Should it be static?
drivers/clk/meson/gxbb.c:1980:12: warning: symbol 'gxbb_cts_parent_names' was not declared. Should it be static?
drivers/clk/meson/gxbb.c:2036:12: warning: symbol 'gxbb_cts_hdmi_tx_parent_names' was not declared. Should it be static?

which looks like nice sparse noise to silence.

It would also be nice to make that table of mux selectors const, is that
possible?

---8<----
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 30fbf8f1f190..b92df222f553 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -1582,7 +1582,7 @@ static struct clk_regmap gxbb_vid_pll_div = {
 	},
 };
 
-const char *gxbb_vid_pll_parent_names[] = { "vid_pll_div", "hdmi_pll" };
+static const char * const gxbb_vid_pll_parent_names[] = { "vid_pll_div", "hdmi_pll" };
 
 static struct clk_regmap gxbb_vid_pll_sel = {
 	.data = &(struct clk_regmap_mux_data){
@@ -1617,7 +1617,7 @@ static struct clk_regmap gxbb_vid_pll = {
 	},
 };
 
-const char *gxbb_vclk_parent_names[] = {
+static const char * const gxbb_vclk_parent_names[] = {
 	"vid_pll", "fclk_div4", "fclk_div3", "fclk_div5", "vid_pll",
 	"fclk_div7", "mpll1",
 };
@@ -1977,7 +1977,7 @@ static struct clk_fixed_factor gxbb_vclk2_div12 = {
 };
 
 static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
-const char *gxbb_cts_parent_names[] = {
+static const char * const gxbb_cts_parent_names[] = {
 	"vclk_div1", "vclk_div2", "vclk_div4", "vclk_div6",
 	"vclk_div12", "vclk2_div1", "vclk2_div2", "vclk2_div4",
 	"vclk2_div6", "vclk2_div12"
@@ -2033,7 +2033,7 @@ static struct clk_regmap gxbb_cts_vdac_sel = {
 
 /* TOFIX: add support for cts_tcon */
 static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
-const char *gxbb_cts_hdmi_tx_parent_names[] = {
+static const char * const gxbb_cts_hdmi_tx_parent_names[] = {
 	"vclk_div1", "vclk_div2", "vclk_div4", "vclk_div6",
 	"vclk_div12", "vclk2_div1", "vclk2_div2", "vclk2_div4",
 	"vclk2_div6", "vclk2_div12"
diff --git a/drivers/clk/meson/vid-pll-div.c b/drivers/clk/meson/vid-pll-div.c
index b3370ea7beac..88af0e282ea0 100644
--- a/drivers/clk/meson/vid-pll-div.c
+++ b/drivers/clk/meson/vid-pll-div.c
@@ -55,8 +55,8 @@ static const struct vid_pll_div vid_pll_div_table[] = {
 #define to_meson_vid_pll_div(_hw) \
 	container_of(_hw, struct meson_vid_pll_div, hw)
 
-const struct vid_pll_div *_get_table_val(unsigned int shift_val,
-					 unsigned int shift_sel)
+static const struct vid_pll_div *_get_table_val(unsigned int shift_val,
+						unsigned int shift_sel)
 {
 	int i;
 


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Re: [GIT PULL] clk: meson: updates for v4.21

[Neil Armstrong]

On 03/12/2018 22:54, Stephen Boyd wrote:
> Quoting Neil Armstrong (2018-11-23 07:23:33)
>> Dear clock maintainers,
>>
>> Below is a request to pull updates for Amlogic clocks.
>>
>> It covers essentially Meson GX Video clocks, Meson8b CPU clocks
>> and 2 bindings changes.
> 
> Pulled into clk-next now.

Thanks !

> 
> I got this when testing:
> 
> drivers/clk/meson/vid-pll-div.c:58:26: warning: symbol '_get_table_val' was not declared. Should it be static?
> drivers/clk/meson/gxbb.c:1585:12: warning: symbol 'gxbb_vid_pll_parent_names' was not declared. Should it be static?
> drivers/clk/meson/gxbb.c:1620:12: warning: symbol 'gxbb_vclk_parent_names' was not declared. Should it be static?
> drivers/clk/meson/gxbb.c:1980:12: warning: symbol 'gxbb_cts_parent_names' was not declared. Should it be static?
> drivers/clk/meson/gxbb.c:2036:12: warning: symbol 'gxbb_cts_hdmi_tx_parent_names' was not declared. Should it be static?
> 
> which looks like nice sparse noise to silence.
> 
> It would also be nice to make that table of mux selectors const, is that
> possible?

I posted a fix for this.

Neil

> 
> ---8<----
> diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
> index 30fbf8f1f190..b92df222f553 100644
> --- a/drivers/clk/meson/gxbb.c
> +++ b/drivers/clk/meson/gxbb.c
> @@ -1582,7 +1582,7 @@ static struct clk_regmap gxbb_vid_pll_div = {
>  	},
>  };
>  
> -const char *gxbb_vid_pll_parent_names[] = { "vid_pll_div", "hdmi_pll" };
> +static const char * const gxbb_vid_pll_parent_names[] = { "vid_pll_div", "hdmi_pll" };
>  
>  static struct clk_regmap gxbb_vid_pll_sel = {
>  	.data = &(struct clk_regmap_mux_data){
> @@ -1617,7 +1617,7 @@ static struct clk_regmap gxbb_vid_pll = {
>  	},
>  };
>  
> -const char *gxbb_vclk_parent_names[] = {
> +static const char * const gxbb_vclk_parent_names[] = {
>  	"vid_pll", "fclk_div4", "fclk_div3", "fclk_div5", "vid_pll",
>  	"fclk_div7", "mpll1",
>  };
> @@ -1977,7 +1977,7 @@ static struct clk_fixed_factor gxbb_vclk2_div12 = {
>  };
>  
>  static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
> -const char *gxbb_cts_parent_names[] = {
> +static const char * const gxbb_cts_parent_names[] = {
>  	"vclk_div1", "vclk_div2", "vclk_div4", "vclk_div6",
>  	"vclk_div12", "vclk2_div1", "vclk2_div2", "vclk2_div4",
>  	"vclk2_div6", "vclk2_div12"
> @@ -2033,7 +2033,7 @@ static struct clk_regmap gxbb_cts_vdac_sel = {
>  
>  /* TOFIX: add support for cts_tcon */
>  static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
> -const char *gxbb_cts_hdmi_tx_parent_names[] = {
> +static const char * const gxbb_cts_hdmi_tx_parent_names[] = {
>  	"vclk_div1", "vclk_div2", "vclk_div4", "vclk_div6",
>  	"vclk_div12", "vclk2_div1", "vclk2_div2", "vclk2_div4",
>  	"vclk2_div6", "vclk2_div12"
> diff --git a/drivers/clk/meson/vid-pll-div.c b/drivers/clk/meson/vid-pll-div.c
> index b3370ea7beac..88af0e282ea0 100644
> --- a/drivers/clk/meson/vid-pll-div.c
> +++ b/drivers/clk/meson/vid-pll-div.c
> @@ -55,8 +55,8 @@ static const struct vid_pll_div vid_pll_div_table[] = {
>  #define to_meson_vid_pll_div(_hw) \
>  	container_of(_hw, struct meson_vid_pll_div, hw)
>  
> -const struct vid_pll_div *_get_table_val(unsigned int shift_val,
> -					 unsigned int shift_sel)
> +static const struct vid_pll_div *_get_table_val(unsigned int shift_val,
> +						unsigned int shift_sel)
>  {
>  	int i;
>  
> 


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