Re: [PATCH 1/7] drivers: clk: meson: Add Amlogic T7 fix pll support

[Jian Hu <jian.hu@amlogic.com>]

On 2/26/2026 10:30 PM, Ronald Claveau wrote:
> [ EXTERNAL EMAIL ]
>
> On 2/18/26 7:05 PM, Jerome Brunet wrote:
>> On mer. 18 févr. 2026 at 11:17, Ronald Claveau <linux-kernel-dev@aliel.fr> wrote:
>>
>>> Add PLL for the clock controller of the Amlogic T7 SoC family.
>>>
>> As Krzysztof pointed out, a series like this needs a cover letter to explain
>> what you are trying to acheive overall, and proper threading.
>>
>> The description above is too vague.
>>
> Indeed, I will do that for the next one.
>
>>> Signed-off-by: Ronald Claveau <linux-kernel-dev@aliel.fr>
>>> ---
>>>   drivers/clk/meson/t7-pll.c | 257 +++++++++++++++++++++++++++++++++++++
>>>   1 file changed, 257 insertions(+)
>>>
>>> diff --git a/drivers/clk/meson/t7-pll.c b/drivers/clk/meson/t7-pll.c
>>> index 0a622f45fa36..3dd3aca50b7c 100644
>>> --- a/drivers/clk/meson/t7-pll.c
>>> +++ b/drivers/clk/meson/t7-pll.c
>>> @@ -71,6 +71,15 @@
>>>   #define MCLK_PLL_CNTL4              0x10
>>>   #define MCLK_PLL_STS                0x14
>>>
>>> +#define FPLL_CTRL0          0x00
>>> +#define FPLL_CTRL1          0x04
>>> +#define FPLL_CTRL2          0x08
>>> +#define FPLL_CTRL3          0x0c
>>> +#define FPLL_CTRL4          0x10
>>> +#define FPLL_CTRL5          0x14
>>> +#define FPLL_CTRL6          0x18
>>> +#define FPLL_STS            0x1c
>> The PLL you are adding is described in the datasheet as the MPLL. FPLL
>> is nowhere to be found. Prefer using names that relate to the
>> documentation.
>>
>> If you must make a name up, you need to have a very good reason and to
>> explain it.
>>
>> Still from the public documentation, this PLL belong in the same device as
>> MPLL0, MPLL1, etc ... BUT, I remember correctly the T7 initial
>> submission, the fixed PLL and fdivs are supposed to be provided through
>> SCMI clocks. Have you checked that ?
>>
> Yes, I read the initial submission, and I tried first with scmi-smc and
> scmi-mailbox, but with no success.
> I will try it again and ask khadas team for more information related to
> this.


The fixed pll and sys clocks registers cannot be accessed in kernel, so 
these clocks are

implemented in the Bootloader BL31.


Please ask the Khadas team to contact Amlogic for the latest Bootloader 
version, then you can use

the fixed pll and fdivs SCMI clocks defined in 
include/dt-bindings/clock/amlogic,t7,scmi.h.

Reference:

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/dt-bindings/clock/amlogic,t7-scmi.h


>>> +
>>>   static const struct pll_mult_range t7_media_pll_mult_range = {
>>>       .min = 125,
>>>       .max = 250,
>>> @@ -1047,6 +1056,253 @@ static const struct meson_clkc_data t7_mclk_data = {
>>>       },
>>>   };
>>>
[...]
>
> --
> Best regards,
> Ronald
>
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