Re: [PATCH v4 0/4] pwm: meson: make full use of common clock framework

[Neil Armstrong <neil.armstrong@linaro.org>]

Hi Heiner,

On 13/04/2023 07:48, Heiner Kallweit wrote:
> Newer versions of the PWM block use a core clock with external mux,
> divider, and gate. These components either don't exist any longer in
> the PWM block, or they are bypassed.
> To minimize needed changes for supporting the new version, the internal
> divider and gate should be handled by CCF too.
> 
> I didn't see a good way to split the patch, therefore it's somewhat
> bigger. What it does:
> 
> - The internal mux is handled by CCF already. Register also internal
>    divider and gate with CCF, so that we have one representation of the
>    input clock: [mux] parent of [divider] parent of [gate]
>    
> - Now that CCF selects an appropriate mux parent, we don't need the
>    DT-provided default parent any longer. Accordingly we can also omit
>    setting the mux parent directly in the driver.
>    
> - Instead of manually handling the pre-div divider value, let CCF
>    set the input clock. Targeted input clock frequency is
>    0xffff * 1/period for best precision.
>    
> - For the "inverted pwm disabled" scenario target an input clock
>    frequency of 1GHz. This ensures that the remaining low pulses
>    have minimum length.
> 
> I don't have hw with the old PWM block, therefore I couldn't test this
> patch. With the not yet included extension for the new PWM block
> (channel->clock directly coming from get_clk(external_clk)) I didn't
> notice any problem. My system uses PWM for the CPU voltage regulator
> and for the SDIO 32kHz clock.

Don't you have any GXBB, GXL, GXM, G12A, SM1 or G12B boards to test on ?

Anyway, I'd like to see a complete test on those SoCs on the actually
used function (mainly 32k output clock for wifi) before seeing this merges
since it's a big change.

> 
> Note: The clock gate in the old PWM block is permanently disabled.
> This seems to indicate that it's not used by the new PWM block.
> 
> Changes to RFT/RFC version:
> - use parent_hws instead of parent_names for div/gate clock
> - use devm_clk_hw_register where the struct clk * returned by
>    devm_clk_register isn't needed
> 
> v2:
> - add patch 1
> - add patch 3
> - switch to using clk_parent_data in all relevant places
> 
> v3:
> - patch 1: move setting mux parent data out of the loop
> - patch 4: add flag CLK_IGNORE_UNUSED
> 
> v4:
> - patch 2: improve commit message
> - patch 4: remove variable tmp in meson_pwm_get_state
> - patch 4: don't use deprecated function devm_clk_register
> 
> Heiner Kallweit (4):
>    pwm: meson: switch to using struct clk_parent_data for mux parents
>    pwm: meson: don't use hdmi/video clock as mux parent
>    pwm: meson: change clk/pwm gate from mask to bit
>    pwm: meson: make full use of common clock framework
> 
>   drivers/pwm/pwm-meson.c | 201 +++++++++++++++++++++-------------------
>   1 file changed, 107 insertions(+), 94 deletions(-)
> 


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