[PATCH v4 0/4] Add PWM support Amlogic S7 S7D S6

[PATCH v4 0/4] Add PWM support Amlogic S7 S7D S6

[Xianwei Zhao via B4 Relay]

Add bindings and driver support Amlogic S7/S7D/S6 SoCs.

Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
Changes in v4:
- It is divided into three submissions based on the function-driven part.
- Merge and modify functions for init clocks, According to Alexandre's suggestion.
- Link to v3: https://lore.kernel.org/r/20260521-s6-s7-pwm-v3-0-57b073fbafef@amlogic.com

Changes in v3:
- Use npwm instead of single_pwm in priv_data and format adjustments.
- Link to v2: https://lore.kernel.org/r/20260402-s6-s7-pwm-v2-0-657dce040956@amlogic.com

Changes in v2:
- Simpler s7 clock desc, and drop the example in bindings.
- Make minor changes to probe based on Martin's suggestion.
- Link to v1: https://lore.kernel.org/r/20260326-s6-s7-pwm-v1-0-67e2f72b98bc@amlogic.com

---
Junyi Zhao (1):
      dt-bindings: pwm: amlogic: Add new bindings for S6 S7 S7D

Xianwei Zhao (3):
      pwm: meson: add the PWM count driver data
      pwm: meson: use bulk API for per-channel clocks
      pwm: meson: Add support for Amlogic S7

 .../devicetree/bindings/pwm/pwm-amlogic.yaml       | 19 ++++++
 drivers/pwm/pwm-meson.c                            | 73 +++++++++++++---------
 2 files changed, 63 insertions(+), 29 deletions(-)
---
base-commit: b1385d0c7b7c633e55adcf4a7c1ef46c43a84a4a
change-id: 20260325-s6-s7-pwm-281658b88736

Best regards,
-- 
Xianwei Zhao <xianwei.zhao@amlogic.com>



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[PATCH v4 1/4] dt-bindings: pwm: amlogic: Add new bindings for S6 S7 S7D

[Xianwei Zhao via B4 Relay]

From: Junyi Zhao <junyi.zhao@amlogic.com>

Amlogic S7/S7D/S6 different from the previous SoCs, a controller
includes one pwm, at the same time, the controller has only one
input clock source.

Signed-off-by: Junyi Zhao <junyi.zhao@amlogic.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
 .../devicetree/bindings/pwm/pwm-amlogic.yaml          | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml b/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml
index c337d85da40f..93fa97f4011b 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml
+++ b/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml
@@ -37,6 +37,7 @@ properties:
       - enum:
           - amlogic,meson8-pwm-v2
           - amlogic,meson-s4-pwm
+          - amlogic,s7-pwm
       - items:
           - enum:
               - amlogic,a4-pwm
@@ -45,6 +46,11 @@ properties:
               - amlogic,t7-pwm
               - amlogic,meson-a1-pwm
           - const: amlogic,meson-s4-pwm
+      - items:
+          - enum:
+              - amlogic,s6-pwm
+              - amlogic,s7d-pwm
+          - const: amlogic,s7-pwm
       - items:
           - enum:
               - amlogic,meson8b-pwm-v2
@@ -146,6 +152,19 @@ allOf:
         clock-names: false
       required:
         - clocks
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - amlogic,s7-pwm
+    then:
+      properties:
+        clocks:
+          maxItems: 1
+        clock-names: false
+      required:
+        - clocks
 
   - if:
       properties:

-- 
2.52.0



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[PATCH v4 2/4] pwm: meson: add the PWM count driver data

[Xianwei Zhao via B4 Relay]

From: Xianwei Zhao <xianwei.zhao@amlogic.com>

Add .npwm fill the  existing entries, use it in probe, and switch the loop
in meson_pwm_init_clocks_meson8b() and meson_pwm_init_channels_s4() to
chip->npwm. No functional change.

Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
 drivers/pwm/pwm-meson.c | 20 ++++++++++++++++----
 1 file changed, 16 insertions(+), 4 deletions(-)

diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c
index 8c6bf3d49753..22cefc6d5dd0 100644
--- a/drivers/pwm/pwm-meson.c
+++ b/drivers/pwm/pwm-meson.c
@@ -113,6 +113,7 @@ struct meson_pwm_data {
 	int (*channels_init)(struct pwm_chip *chip);
 	bool has_constant;
 	bool has_polarity;
+	u8 npwm;
 };
 
 struct meson_pwm {
@@ -382,7 +383,7 @@ static int meson_pwm_init_clocks_meson8b(struct pwm_chip *chip,
 	char name[255];
 	int err;
 
-	for (i = 0; i < MESON_NUM_PWMS; i++) {
+	for (i = 0; i < chip->npwm; i++) {
 		struct meson_pwm_channel *channel = &meson->channels[i];
 		struct clk_parent_data div_parent = {}, gate_parent = {};
 		struct clk_init_data init = {};
@@ -510,7 +511,7 @@ static int meson_pwm_init_channels_s4(struct pwm_chip *chip)
 	struct meson_pwm *meson = to_meson_pwm(chip);
 	int i, ret;
 
-	for (i = 0; i < MESON_NUM_PWMS; i++) {
+	for (i = 0; i < chip->npwm; i++) {
 		meson->channels[i].clk = of_clk_get(np, i);
 		if (IS_ERR(meson->channels[i].clk))
 			return dev_err_probe(dev,
@@ -530,6 +531,7 @@ static int meson_pwm_init_channels_s4(struct pwm_chip *chip)
 static const struct meson_pwm_data pwm_meson8b_data = {
 	.parent_names = { "xtal", NULL, "fclk_div4", "fclk_div3" },
 	.channels_init = meson_pwm_init_channels_meson8b_legacy,
+	.npwm = 2,
 };
 
 /*
@@ -539,6 +541,7 @@ static const struct meson_pwm_data pwm_meson8b_data = {
 static const struct meson_pwm_data pwm_gxbb_ao_data = {
 	.parent_names = { "xtal", "clk81", NULL, NULL },
 	.channels_init = meson_pwm_init_channels_meson8b_legacy,
+	.npwm = 2,
 };
 
 static const struct meson_pwm_data pwm_axg_ee_data = {
@@ -546,6 +549,7 @@ static const struct meson_pwm_data pwm_axg_ee_data = {
 	.channels_init = meson_pwm_init_channels_meson8b_legacy,
 	.has_constant = true,
 	.has_polarity = true,
+	.npwm = 2,
 };
 
 static const struct meson_pwm_data pwm_axg_ao_data = {
@@ -553,6 +557,7 @@ static const struct meson_pwm_data pwm_axg_ao_data = {
 	.channels_init = meson_pwm_init_channels_meson8b_legacy,
 	.has_constant = true,
 	.has_polarity = true,
+	.npwm = 2,
 };
 
 static const struct meson_pwm_data pwm_g12a_ee_data = {
@@ -560,6 +565,7 @@ static const struct meson_pwm_data pwm_g12a_ee_data = {
 	.channels_init = meson_pwm_init_channels_meson8b_legacy,
 	.has_constant = true,
 	.has_polarity = true,
+	.npwm = 2,
 };
 
 static const struct meson_pwm_data pwm_g12a_ao_ab_data = {
@@ -567,6 +573,7 @@ static const struct meson_pwm_data pwm_g12a_ao_ab_data = {
 	.channels_init = meson_pwm_init_channels_meson8b_legacy,
 	.has_constant = true,
 	.has_polarity = true,
+	.npwm = 2,
 };
 
 static const struct meson_pwm_data pwm_g12a_ao_cd_data = {
@@ -574,22 +581,26 @@ static const struct meson_pwm_data pwm_g12a_ao_cd_data = {
 	.channels_init = meson_pwm_init_channels_meson8b_legacy,
 	.has_constant = true,
 	.has_polarity = true,
+	.npwm = 2,
 };
 
 static const struct meson_pwm_data pwm_meson8_v2_data = {
 	.channels_init = meson_pwm_init_channels_meson8b_v2,
+	.npwm = 2,
 };
 
 static const struct meson_pwm_data pwm_meson_axg_v2_data = {
 	.channels_init = meson_pwm_init_channels_meson8b_v2,
 	.has_constant = true,
 	.has_polarity = true,
+	.npwm = 2,
 };
 
 static const struct meson_pwm_data pwm_s4_data = {
 	.channels_init = meson_pwm_init_channels_s4,
 	.has_constant = true,
 	.has_polarity = true,
+	.npwm = 2,
 };
 
 static const struct of_device_id meson_pwm_matches[] = {
@@ -650,9 +661,10 @@ static int meson_pwm_probe(struct platform_device *pdev)
 {
 	struct pwm_chip *chip;
 	struct meson_pwm *meson;
+	const struct meson_pwm_data *pdata = of_device_get_match_data(&pdev->dev);
 	int err;
 
-	chip = devm_pwmchip_alloc(&pdev->dev, MESON_NUM_PWMS, sizeof(*meson));
+	chip = devm_pwmchip_alloc(&pdev->dev, pdata->npwm, sizeof(*meson));
 	if (IS_ERR(chip))
 		return PTR_ERR(chip);
 	meson = to_meson_pwm(chip);
@@ -664,7 +676,7 @@ static int meson_pwm_probe(struct platform_device *pdev)
 	spin_lock_init(&meson->lock);
 	chip->ops = &meson_pwm_ops;
 
-	meson->data = of_device_get_match_data(&pdev->dev);
+	meson->data = pdata;
 
 	err = meson->data->channels_init(chip);
 	if (err < 0)

-- 
2.52.0



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[PATCH v4 3/4] pwm: meson: use bulk API for per-channel clocks

[Xianwei Zhao via B4 Relay]

From: Xianwei Zhao <xianwei.zhao@amlogic.com>

The S4 PWM driver currently gets each channel clock individually with
of_clk_get() and uses a custom cleanup action to release the clocks.

Use devm_clk_bulk_get_all() instead to retrieve all per-channel clocks
at once. Verify that the number of clocks matches the number of PWM
channels and assign each clock to its corresponding channel.

This also allows the per-channel clock initialization code to be shared
by Meson PWM variants using one clock per channel.

Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
 drivers/pwm/pwm-meson.c | 40 ++++++++++++++++------------------------
 1 file changed, 16 insertions(+), 24 deletions(-)

diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c
index 22cefc6d5dd0..6f151464d7cc 100644
--- a/drivers/pwm/pwm-meson.c
+++ b/drivers/pwm/pwm-meson.c
@@ -497,33 +497,25 @@ static int meson_pwm_init_channels_meson8b_v2(struct pwm_chip *chip)
 	return meson_pwm_init_clocks_meson8b(chip, mux_parent_data);
 }
 
-static void meson_pwm_s4_put_clk(void *data)
-{
-	struct clk *clk = data;
-
-	clk_put(clk);
-}
-
-static int meson_pwm_init_channels_s4(struct pwm_chip *chip)
+static int meson_pwm_init_channels_per_channel_clk(struct pwm_chip *chip)
 {
 	struct device *dev = pwmchip_parent(chip);
-	struct device_node *np = dev->of_node;
 	struct meson_pwm *meson = to_meson_pwm(chip);
-	int i, ret;
+	struct clk_bulk_data *clks;
+	unsigned int i;
+	int num;
 
-	for (i = 0; i < chip->npwm; i++) {
-		meson->channels[i].clk = of_clk_get(np, i);
-		if (IS_ERR(meson->channels[i].clk))
-			return dev_err_probe(dev,
-					     PTR_ERR(meson->channels[i].clk),
-					     "Failed to get clk\n");
-
-		ret = devm_add_action_or_reset(dev, meson_pwm_s4_put_clk,
-					       meson->channels[i].clk);
-		if (ret)
-			return dev_err_probe(dev, ret,
-					     "Failed to add clk_put action\n");
-	}
+	num = devm_clk_bulk_get_all(dev, &clks);
+	if (num < 0)
+		return dev_err_probe(dev, num, "Failed to get clocks\n");
+
+	if (num != chip->npwm)
+		return dev_err_probe(dev, -EINVAL,
+				"expected %u clocks, got %d\n",
+				chip->npwm, num);
+
+	for (i = 0; i < chip->npwm; i++)
+		meson->channels[i].clk = clks[i].clk;
 
 	return 0;
 }
@@ -597,7 +589,7 @@ static const struct meson_pwm_data pwm_meson_axg_v2_data = {
 };
 
 static const struct meson_pwm_data pwm_s4_data = {
-	.channels_init = meson_pwm_init_channels_s4,
+	.channels_init = meson_pwm_init_channels_per_channel_clk,
 	.has_constant = true,
 	.has_polarity = true,
 	.npwm = 2,

-- 
2.52.0



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[PATCH v4 4/4] pwm: meson: Add support for Amlogic S7

[Xianwei Zhao via B4 Relay]

From: Xianwei Zhao <xianwei.zhao@amlogic.com>

Add support for Amlogic S7 PWM. Amlogic S7 different from the previous
SoCs, a controller includes one pwm, at the same time,the controller has
only one input clock source.

Also use the kernel coding style for the empty of_device_id terminator.

Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
 drivers/pwm/pwm-meson.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c
index 6f151464d7cc..2da958231719 100644
--- a/drivers/pwm/pwm-meson.c
+++ b/drivers/pwm/pwm-meson.c
@@ -595,6 +595,13 @@ static const struct meson_pwm_data pwm_s4_data = {
 	.npwm = 2,
 };
 
+static const struct meson_pwm_data pwm_s7_data = {
+	.channels_init = meson_pwm_init_channels_per_channel_clk,
+	.has_constant = true,
+	.has_polarity = true,
+	.npwm = 1,
+};
+
 static const struct of_device_id meson_pwm_matches[] = {
 	{
 		.compatible = "amlogic,meson8-pwm-v2",
@@ -645,7 +652,11 @@ static const struct of_device_id meson_pwm_matches[] = {
 		.compatible = "amlogic,meson-s4-pwm",
 		.data = &pwm_s4_data
 	},
-	{},
+	{
+		.compatible = "amlogic,s7-pwm",
+		.data = &pwm_s7_data
+	},
+	{ }
 };
 MODULE_DEVICE_TABLE(of, meson_pwm_matches);
 

-- 
2.52.0



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Re: [PATCH v4 2/4] pwm: meson: add the PWM count driver data

[Alexandre Mergnat]

> Add .npwm fill the  existing entries, use it in probe, and switch the loop
> in meson_pwm_init_clocks_meson8b() and meson_pwm_init_channels_s4() to
> chip->npwm. No functional change.
> 
> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
>
> diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c
> index 8c6bf3d49753..22cefc6d5dd0 100644
> --- a/drivers/pwm/pwm-meson.c
> +++ b/drivers/pwm/pwm-meson.c
> @@ -113,6 +113,7 @@ struct meson_pwm_data {
>  	int (*channels_init)(struct pwm_chip *chip);

The commit message has a small typo ("Add .npwm fill the  existing entries" has
a double space.

beside that:
Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>

-- 
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Re: [PATCH v4 3/4] pwm: meson: use bulk API for per-channel clocks

[Alexandre Mergnat]

> The S4 PWM driver currently gets each channel clock individually with
> of_clk_get() and uses a custom cleanup action to release the clocks.
> 
> Use devm_clk_bulk_get_all() instead to retrieve all per-channel clocks
> at once. Verify that the number of clocks matches the number of PWM
> channels and assign each clock to its corresponding channel.
> 
> This also allows the per-channel clock initialization code to be shared
> by Meson PWM variants using one clock per channel.
> 
> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
>
> diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c
> index 22cefc6d5dd0..6f151464d7cc 100644
> --- a/drivers/pwm/pwm-meson.c
> +++ b/drivers/pwm/pwm-meson.c
> @@ -497,33 +497,25 @@ static int meson_pwm_init_channels_meson8b_v2(struct pwm_chip *chip)
>  	return meson_pwm_init_clocks_meson8b(chip, mux_parent_data);
>  }
>  
> -static void meson_pwm_s4_put_clk(void *data)
> -{
> -	struct clk *clk = data;
> -
> -	clk_put(clk);
> -}
> -
> -static int meson_pwm_init_channels_s4(struct pwm_chip *chip)
> +static int meson_pwm_init_channels_per_channel_clk(struct pwm_chip *chip)
>  {
>  	struct device *dev = pwmchip_parent(chip);
> -	struct device_node *np = dev->of_node;
>  	struct meson_pwm *meson = to_meson_pwm(chip);
> -	int i, ret;
> +	struct clk_bulk_data *clks;
> +	unsigned int i;
> +	int num;
>  
> -	for (i = 0; i < chip->npwm; i++) {
> -		meson->channels[i].clk = of_clk_get(np, i);
> -		if (IS_ERR(meson->channels[i].clk))
> -			return dev_err_probe(dev,
> -					     PTR_ERR(meson->channels[i].clk),
> -					     "Failed to get clk\n");
> -
> -		ret = devm_add_action_or_reset(dev, meson_pwm_s4_put_clk,
> -					       meson->channels[i].clk);
> -		if (ret)
> -			return dev_err_probe(dev, ret,
> -					     "Failed to add clk_put action\n");
> -	}
> +	num = devm_clk_bulk_get_all(dev, &clks);
> +	if (num < 0)
> +		return dev_err_probe(dev, num, "Failed to get clocks\n");
> +
> +	if (num != chip->npwm)
> +		return dev_err_probe(dev, -EINVAL,
> +				"expected %u clocks, got %d\n",

Small style nit: the continuation arguments are not aligned with the open
parenthesis, whereas the dev_err_probe() just above and the rest of the driver
do align them. Can you fix it please ?

After that,
Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>

-- 
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Re: [PATCH v4 4/4] pwm: meson: Add support for Amlogic S7

[Alexandre Mergnat]

> Add support for Amlogic S7 PWM. Amlogic S7 different from the previous
> SoCs, a controller includes one pwm, at the same time,the controller has
> only one input clock source.
> 
> Also use the kernel coding style for the empty of_device_id terminator.
> 
> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>

Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>

-- 
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Re: [PATCH v4 3/4] pwm: meson: use bulk API for per-channel clocks

[Uwe Kleine-König]

[-- Attachment #1.1: Type: text/plain, Size: 2679 bytes --]

Hello,

On Mon, Sep 07, 2026 at 05:22:44PM +0200, Alexandre Mergnat wrote:
> > The S4 PWM driver currently gets each channel clock individually with
> > of_clk_get() and uses a custom cleanup action to release the clocks.
> > 
> > Use devm_clk_bulk_get_all() instead to retrieve all per-channel clocks
> > at once. Verify that the number of clocks matches the number of PWM
> > channels and assign each clock to its corresponding channel.
> > 
> > This also allows the per-channel clock initialization code to be shared
> > by Meson PWM variants using one clock per channel.
> > 
> > Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
> >
> > diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c
> > index 22cefc6d5dd0..6f151464d7cc 100644
> > --- a/drivers/pwm/pwm-meson.c
> > +++ b/drivers/pwm/pwm-meson.c
> > @@ -497,33 +497,25 @@ static int meson_pwm_init_channels_meson8b_v2(struct pwm_chip *chip)
> >  	return meson_pwm_init_clocks_meson8b(chip, mux_parent_data);
> >  }
> >  
> > -static void meson_pwm_s4_put_clk(void *data)
> > -{
> > -	struct clk *clk = data;
> > -
> > -	clk_put(clk);
> > -}
> > -
> > -static int meson_pwm_init_channels_s4(struct pwm_chip *chip)
> > +static int meson_pwm_init_channels_per_channel_clk(struct pwm_chip *chip)
> >  {
> >  	struct device *dev = pwmchip_parent(chip);
> > -	struct device_node *np = dev->of_node;
> >  	struct meson_pwm *meson = to_meson_pwm(chip);
> > -	int i, ret;
> > +	struct clk_bulk_data *clks;
> > +	unsigned int i;
> > +	int num;
> >  
> > -	for (i = 0; i < chip->npwm; i++) {
> > -		meson->channels[i].clk = of_clk_get(np, i);
> > -		if (IS_ERR(meson->channels[i].clk))
> > -			return dev_err_probe(dev,
> > -					     PTR_ERR(meson->channels[i].clk),
> > -					     "Failed to get clk\n");
> > -
> > -		ret = devm_add_action_or_reset(dev, meson_pwm_s4_put_clk,
> > -					       meson->channels[i].clk);
> > -		if (ret)
> > -			return dev_err_probe(dev, ret,
> > -					     "Failed to add clk_put action\n");
> > -	}
> > +	num = devm_clk_bulk_get_all(dev, &clks);
> > +	if (num < 0)
> > +		return dev_err_probe(dev, num, "Failed to get clocks\n");
> > +
> > +	if (num != chip->npwm)
> > +		return dev_err_probe(dev, -EINVAL,
> > +				"expected %u clocks, got %d\n",
> 
> Small style nit: the continuation arguments are not aligned with the open
> parenthesis, whereas the dev_err_probe() just above and the rest of the driver
> do align them. Can you fix it please ?

No need to resend for that, I can fix that up while applying (after
checking I don't have further concerns).

Thanks Alex for your review!

Best regards
Uwe

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