* [PATCH V3 3/3] ARM: dts: Add pcie controller node for Samsung EXYNOS5440 SoC
@ 2013-06-07 9:24 Jingoo Han
0 siblings, 0 replies; only message in thread
From: Jingoo Han @ 2013-06-07 9:24 UTC (permalink / raw)
To: 'Kukjin Kim', 'Bjorn Helgaas'
Cc: linux-samsung-soc, linux-pci, devicetree-discuss,
linux-arm-kernel, linux-kernel, 'Grant Likely',
'Andrew Murray', 'Thomas Petazzoni',
'Thierry Reding', 'Jason Gunthorpe',
'Surendranath Gurivireddy Balla',
'Siva Reddy Kallam', 'Thomas Abraham',
Jingoo Han
Exynos5440 has two PCIe controllers which can be used as root complex
for PCIe interface.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
---
arch/arm/boot/dts/exynos5440-ssdk5440.dts | 8 ++++++++
arch/arm/boot/dts/exynos5440.dtsi | 32 +++++++++++++++++++++++++++++
2 files changed, 40 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
index d55042b..efe7d39 100644
--- a/arch/arm/boot/dts/exynos5440-ssdk5440.dts
+++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
@@ -30,4 +30,12 @@
clock-frequency = <50000000>;
};
};
+
+ pcie0@40000000 {
+ reset-gpio = <5>;
+ };
+
+ pcie1@60000000 {
+ reset-gpio = <22>;
+ };
};
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index f6b1c89..ea37e94 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -216,4 +216,36 @@
clock-names = "rtc";
status = "disabled";
};
+
+ pcie0@40000000 {
+ compatible = "samsung,exynos5440-pcie";
+ reg = <0x40000000 0x4000
+ 0x290000 0x1000
+ 0x270000 0x1000
+ 0x271000 0x40>;
+ interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xf>;
+ ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00200000 /* configuration space */
+ 0x81000000 0 0 0x40200000 0 0x00004000 /* downstream I/O */
+ 0x82000000 0 0 0x40204000 0 0x10000000>; /* non-prefetchable memory */
+ };
+
+ pcie1@60000000 {
+ compatible = "samsung,exynos5440-pcie";
+ reg = <0x60000000 0x4000
+ 0x2a0000 0x1000
+ 0x272000 0x1000
+ 0x271040 0x40>;
+ interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xf>;
+ ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00200000 /* configuration space */
+ 0x81000000 0 0 0x60200000 0 0x00004000 /* downstream I/O */
+ 0x82000000 0 0 0x60204000 0 0x10000000>; /* non-prefetchable memory */
+ };
};
--
1.7.10.4
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